From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Feb 2021 12:27:08 +0000 (+0000)
Subject: add SVP64 TestIssuer separate unit test
X-Git-Tag: convert-csv-opcode-to-binary~235
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aaaf24c6f41801d9f270589b62277179f724dee5;p=soc.git

add SVP64 TestIssuer separate unit test
---

diff --git a/src/soc/fu/alu/svp64_cases.py b/src/soc/fu/alu/svp64_cases.py
deleted file mode 100644
index f6ed2720..00000000
--- a/src/soc/fu/alu/svp64_cases.py
+++ /dev/null
@@ -1,30 +0,0 @@
-import random
-from soc.fu.test.common import (TestCase, TestAccumulatorBase)
-from soc.config.endian import bigendian
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import special_sprs
-from soc.sv.trans.svp64 import SVP64Asm
-
-
-class ALUTestCase(TestAccumulatorBase):
-
-    def case_1_sv_add(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
-        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
-                       ])
-        lst = list(isa)
-        print ("listing", lst)
-        initial_regs = [0] * 32
-        initial_regs[9] = 0x1234
-        initial_regs[10] = 0x1111
-        initial_regs[5] = 0x4321
-        initial_regs[6] = 0x2223
-        svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
-
-        self.add_case(Program(lst, bigendian), initial_regs,
-                      initial_svstate=svstate)
diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
new file mode 100644
index 00000000..bf785010
--- /dev/null
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -0,0 +1,30 @@
+import random
+from soc.fu.test.common import (TestCase, TestAccumulatorBase)
+from soc.config.endian import bigendian
+from soc.simulator.program import Program
+from soc.decoder.isa.caller import special_sprs
+from soc.sv.trans.svp64 import SVP64Asm
+
+
+class SVP64ALUTestCase(TestAccumulatorBase):
+
+    def case_1_sv_add(self):
+        # adds:
+        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
+        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
+        isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
+                       ])
+        lst = list(isa)
+        print ("listing", lst)
+        initial_regs = [0] * 32
+        initial_regs[9] = 0x1234
+        initial_regs[10] = 0x1111
+        initial_regs[5] = 0x4321
+        initial_regs[6] = 0x2223
+        svstate = SVP64State()
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)
diff --git a/src/soc/simple/test/test_issuer_svp64.py b/src/soc/simple/test/test_issuer_svp64.py
new file mode 100644
index 00000000..3e64f7a9
--- /dev/null
+++ b/src/soc/simple/test/test_issuer_svp64.py
@@ -0,0 +1,24 @@
+"""test of SVP64 operations.
+
+related bugs:
+
+ * https://bugs.libre-soc.org/show_bug.cgi?id=363
+"""
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+
+import unittest
+from soc.simple.test.test_runner import TestRunner
+
+# test with ALU data and Logical data
+from soc.fu.alu.test.svp64_cases import SVP64ALUTestCase
+
+
+if __name__ == "__main__":
+    unittest.main(exit=False)
+    suite = unittest.TestSuite()
+    suite.addTest(TestRunner(SVP64ALUTestCase().test_data))
+
+    runner = unittest.TextTestRunner()
+    runner.run(suite)