From: Luke Kenneth Casson Leighton Date: Thu, 11 Jun 2020 10:54:27 +0000 (+0100) Subject: must distinguish between rd/write xer_ca sim helpers X-Git-Tag: div_pipeline~396 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aabc88c39e0fb280ef3586b718df5db836734436;p=soc.git must distinguish between rd/write xer_ca sim helpers --- diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index 3cc37ce6..51adba38 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -27,7 +27,7 @@ def get_cu_inputs(dec2, sim): yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC - yield from ALUHelpers.get_sim_xer_ca(res, sim, dec2) # XER.ca + yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca print ("inputs", res) @@ -248,7 +248,7 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) ALUHelpers.check_xer_ca(self, res, sim_o, code)