From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 13 Sep 2012 11:18:03 +0000 (+0200)
Subject: add test_MigIo.py for de0_nano and de1 example
X-Git-Tag: 24jan2021_ls180~2575^2~146
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aac16a9e11c10ff8a6663cdd4cd6aefa473e485b;p=litex.git

add test_MigIo.py for de0_nano and de1 example
---

diff --git a/examples/de0_nano/client/test_MigIo.py b/examples/de0_nano/client/test_MigIo.py
new file mode 100644
index 00000000..5eee23cf
--- /dev/null
+++ b/examples/de0_nano/client/test_MigIo.py
@@ -0,0 +1,55 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.bus.transactions import *
+from migen.bank import description, csrgen
+from migen.bank.description import *
+
+import sys
+sys.path.append("../../../")
+
+from migScope import trigger, recorder, migIo
+import spi2Csr
+from spi2Csr.tools.uart2Spi import *
+
+#==============================================================================
+#	P A R A M E T E R S
+#==============================================================================
+# Bus Width
+trig_width = 16
+dat_width = 16
+
+# Record Size
+record_size = 1024
+
+# Csr Addr
+MIGIO0_ADDR  = 0x0000
+TRIGGER_ADDR  = 0x0200
+RECORDER_ADDR = 0x0400
+
+# MigScope Configuration
+# migIo
+migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
+
+# Trigger
+term0 = trigger.Term(trig_width)
+trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
+
+# Recorder
+recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
+
+#==============================================================================
+#                  T E S T  M I G I O 
+#==============================================================================
+
+csr = Uart2Spi(1,115200)
+
+print("1) Write Led Reg")
+for i in range(10):
+	csr.write(MIGIO0_ADDR + 0,0xA5)
+	time.sleep(0.1)
+	csr.write(MIGIO0_ADDR + 0,0x5A)
+	time.sleep(0.1)
+	
+print("2) Read Switch Reg")
+print(csr.read(MIGIO0_ADDR + 1))
diff --git a/examples/de1/client/test_MigIo.py b/examples/de1/client/test_MigIo.py
new file mode 100644
index 00000000..5eee23cf
--- /dev/null
+++ b/examples/de1/client/test_MigIo.py
@@ -0,0 +1,55 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.bus.transactions import *
+from migen.bank import description, csrgen
+from migen.bank.description import *
+
+import sys
+sys.path.append("../../../")
+
+from migScope import trigger, recorder, migIo
+import spi2Csr
+from spi2Csr.tools.uart2Spi import *
+
+#==============================================================================
+#	P A R A M E T E R S
+#==============================================================================
+# Bus Width
+trig_width = 16
+dat_width = 16
+
+# Record Size
+record_size = 1024
+
+# Csr Addr
+MIGIO0_ADDR  = 0x0000
+TRIGGER_ADDR  = 0x0200
+RECORDER_ADDR = 0x0400
+
+# MigScope Configuration
+# migIo
+migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
+
+# Trigger
+term0 = trigger.Term(trig_width)
+trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
+
+# Recorder
+recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
+
+#==============================================================================
+#                  T E S T  M I G I O 
+#==============================================================================
+
+csr = Uart2Spi(1,115200)
+
+print("1) Write Led Reg")
+for i in range(10):
+	csr.write(MIGIO0_ADDR + 0,0xA5)
+	time.sleep(0.1)
+	csr.write(MIGIO0_ADDR + 0,0x5A)
+	time.sleep(0.1)
+	
+print("2) Read Switch Reg")
+print(csr.read(MIGIO0_ADDR + 1))