From: lkcl Date: Fri, 13 Nov 2020 22:03:23 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1836 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aac508805cf67524f0f38b6c3491e4b2a5feac56;p=libreriscv.git --- diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn index 132a93e9a..22a993bdc 100644 --- a/openpower/sv/major_opcode_allocation.mdwn +++ b/openpower/sv/major_opcode_allocation.mdwn @@ -7,15 +7,14 @@ Consequently rather than settle for a v3.1 32 bit prefix, 8 major opcodes are ta * Taking 8 arbitrary unused major opcodes as-is * Moving anything in the range 0-7 elsewhere -This **only** in "LibreSOC Mode". Candidates for moving elsewhere include twi and tdi. +This **only** in "LibreSOC Mode". Candidates for moving elsewhere include mulli, twi and tdi. -* 2 opcodes are required in order to give SV-P48 the 11 bits needed for prefixing -* 2 opcodes are likewise required for SV-P64 to have 27 bits available -* Ideally 2 opcodes would also be reserved for SV-C32 (prefixing of 16-bit Compressed instructions) -* 1 opcode for 16-bit Compressed instructions -* 1 opcode for SV VBLOCK +* 2 opcodes for 16-bit Compressed instructions with 11 bits available +* 2 opcodes are required in order to give SV-P48 (and SV-C32) the 11 bits needed for prefixing +* 2 opcodes are likewise required for SV-P64 (and SV-C48) to have 27 bits available +* 2 opcodes for SV VBLOCK -With only one opcode for 16-bit Compressed, this only leaves 10 available bits and consequently it may be better to use the opportunity to switch into "16 bit mode". Interestingly SV-P32 could likewise switch into the same. +With only 11 bits for 16-bit Compressed, it may be better to use the opportunity to switch into "16 bit mode". Interestingly SV-P32 could likewise switch into the same. # LE/BE complications. @@ -39,7 +38,7 @@ With the Major Opcode then always being in the 1st 2 bytes it becomes much simpl This one is a conundrum. OpenPOWER ISA was never designed with 16 bit in mind. VLE was added 10 years ago but only by way of marking an entire 64k page as "VLE". With no means to mix 32 bit and 16 bit, jumping between the two would have been painful and taken up space. -Here, in order to embed 16 bit into a predominantly 32 bit stream the overhead of using an entire 16 bits just to switch into Compressed mode is itself a significant overhead. The situation is made worse by 6 bits being taken up by Major Opcode space, leaving only 10 bits to allocate to actual instructions. +Here, in order to embed 16 bit into a predominantly 32 bit stream the overhead of using an entire 16 bits just to switch into Compressed mode is itself a significant overhead. The situation is made worse by 5 bits being taken up by Major Opcode space, leaving only 11 bits to allocate to actual instructions. In addition we would like to add SV-C32 which is a Vectorised version of 16 bit Compressed, and ideally have a variant that adds the 27-bit prefix format from SV-P64, as well. @@ -56,14 +55,14 @@ This latter would be useful in the Vector context to have an alternative meaning |16 bit opcode alt vec. mode ^ | | extra vector prefix if alt set| -Using a major opcode to enter 16 bit mode, leaves 10 bits to find something to use them for: +Using a major opcode to enter 16 bit mode, leaves 11 bits to find something to use them for: 0 1 2 3 4 5 6 7 8 9 a b c d e f | - |major op | what to do here 1 | + |major op | what to do here 1 | |16 bit stay in 16bit mode 1 | |16 bit stay in 16bit mode 1 | |16 bit exit 16bit mode 0 | -One possibility is that the 10 bits are used for bank selection, with some room for additional context such as altering the registers used for the 16 bit operations (bank selection of which scalar regs) +One possibility is that the 11 bits are used for bank selection, with some room for additional context such as altering the registers used for the 16 bit operations (bank selection of which scalar regs) -Another is to use the 10 bits for only the utmost commonly used instructions. That being the case then even one of those 10 bits would also need to be dedicated to saying if 16 bit mode is to be continued. 9 bits remain for actual opcodes! +Another is to use the 11 bits for only the utmost commonly used instructions. That being the case then even one of those 11 bits would also need to be dedicated to saying if 16 bit mode is to be continued. 10 bits remain for actual opcodes!