From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 24 Dec 2014 11:56:05 +0000 (+0100)
Subject: Added "dfflibmap -prepare" help
X-Git-Tag: yosys-0.5~229
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aad195b88ce55d46fe741b217efc66b3aa259535;p=yosys.git

Added "dfflibmap -prepare" help
---

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 58f0c2542..cc6f97c7e 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -457,7 +457,7 @@ struct DfflibmapPass : public Pass {
 	virtual void help()
 	{
 		log("\n");
-		log("    dfflibmap -liberty <file> [selection]\n");
+		log("    dfflibmap [-prepare] -liberty <file> [selection]\n");
 		log("\n");
 		log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
 		log("library specified in the given liberty file.\n");
@@ -465,6 +465,10 @@ struct DfflibmapPass : public Pass {
 		log("This pass may add inverters as needed. Therefore it is recommended to\n");
 		log("first run this pass and then map the logic paths to the target technology.\n");
 		log("\n");
+		log("When called with -prepare, this command will convert the internal FF cells\n");
+		log("to the internal cell types that best match the cells found in the given\n");
+		log("liberty file.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{