From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Mon, 22 Apr 2019 01:19:34 +0000 (-0700)
Subject: Add output signal to PLRU
X-Git-Tag: div_pipeline~2197
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aade6cadcc425feddbdd200de00f1f27e2717d72;p=soc.git

Add output signal to PLRU
---

diff --git a/TLB/src/ariane/plru.py b/TLB/src/ariane/plru.py
index 50951c1f..ff52aace 100644
--- a/TLB/src/ariane/plru.py
+++ b/TLB/src/ariane/plru.py
@@ -24,6 +24,7 @@ class PLRU:
         # Tree (bit per entry)
         self.TLBSZ = 2*(self.entries-1)
         self.plru_tree = Signal(self.TLBSZ)
+        self.plru_tree_o = Signal(self.TLBSZ)
 
     def elaborate(self, platform):
         m = Module()
@@ -58,7 +59,7 @@ class PLRU:
                     plru_idx = idx_base + (i >> shift)
                     print ("plru", i, lvl, hex(idx_base),
                                   plru_idx, shift, new_idx)
-                    m.d.sync += self.plru_tree[plru_idx].eq(new_idx)
+                    m.d.sync += self.plru_tree_o[plru_idx].eq(new_idx)
 
         # Decode tree to write enable signals
         # Next for-loop basically creates the following logic for e.g.