From: Tobias Platen Date: Fri, 29 Oct 2021 16:45:47 +0000 (+0200) Subject: fix unittest test_compldst_multi_mmu.py (load now returned byte previously stored) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aaeac96c002873948dc0f36bb9f9009d00f16f75;p=soc.git fix unittest test_compldst_multi_mmu.py (load now returned byte previously stored) --- diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 833112e3..c14e3537 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -714,24 +714,24 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False, if update: yield from wait_for(dut.wr.rel_o[1]) - yield dut.wr.go.eq(0b10) + yield dut.wr.go_i.eq(0b10) yield addr = yield dut.addr_o print("addr", addr) - yield dut.wr.go.eq(0) + yield dut.wr.go_i.eq(0) else: addr = None yield from wait_for(dut.wr.rel_o[0], test1st=True) - yield dut.wr.go.eq(1) + yield dut.wr.go_i.eq(1) yield - data = yield dut.o_data - print(data) - yield dut.wr.go.eq(0) + data = yield dut.o_data.o + data_ok = yield dut.o_data.o_ok + yield dut.wr.go_i.eq(0) yield from wait_for(dut.busy_o) yield # wait_for(dut.stwd_mem_o) - return data, addr + return data, data_ok, addr def ldst_sim(dut): diff --git a/src/soc/experiment/test/test_compldst_multi_mmu.py b/src/soc/experiment/test/test_compldst_multi_mmu.py index 63f9854e..52397262 100644 --- a/src/soc/experiment/test/test_compldst_multi_mmu.py +++ b/src/soc/experiment/test/test_compldst_multi_mmu.py @@ -35,10 +35,15 @@ from soc.experiment.test.test_wishbone import wb_get def ldst_sim(dut): yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table addr = 0x100e0 - data = 0xf553b658ba7e1f51 + data = 0xFF #just a single byte for this test + #data = 0xf553b658ba7e1f51 yield from store(dut, addr, 0, data, 0) yield + ld_data, data_ok, addr = yield from load(dut, addr, 0, 0) + print("ret") + print(data,data_ok,addr) + assert(ld_data==data) #TODO dut.stop = True # stop simulation