From: lkcl Date: Fri, 17 Nov 2023 20:48:07 +0000 (+0000) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aaee34d792d37ab93d0cc10c3101e0ad7e89f654;p=libreriscv.git --- diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index c50457fb0..02bede7be 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -610,4 +610,25 @@ regarded as worthwhile for much larger integers. # Conclusion -TODO +The majority of ISAs do not have 3-in 2-out instructions for very good +reasons: they are horrendously expensive if implemented as operations +that can write to two registers every clock cycle. Implementations +that take two clock cycles to write to a single write port are frowned-upon, +and the Hazard Management complexity also goes up. + +However when looked at from a Vectorised perspective and using "chaining" +(64-bit carry-out becomes the 64-bit output for the next operation) then +"Operand Forwarding" makes one read and one write effectively disappear, +reducing most of the operations to a manageable efficent 2-in 1-out. +In normal Scalar hardware being used to attempt Vectored bigint operations +the opportunity for "Forwarding" is quite hard to spot, but because of the +Vectorisation it is known *in advance* that a Vector of values is being used, +i.e. only *one* instruction issued not several. Therefore it is easy to +micro-code the Operand Forwarding. + +In essence by taking things that extra step further the complexity of +Scalar ISAs disappears through the introduction of some uniform Vector-Looping +that, although complex in itself in hardware, at least only has to be done once +and becomes uniform-RISC applicable to *all* instructions. These comprehensive +powerful Scalar arithmetic instructions will significantly reduce the +complexity of big-integer operations.