From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Apr 2020 21:13:03 +0000 (+0100)
Subject: add <-iea operator
X-Git-Tag: div_pipeline~1506
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aafcdcf51621d7533e96742119757c70d628b438;p=soc.git

add <-iea operator
---

diff --git a/src/soc/decoder/pseudo/lexer.py b/src/soc/decoder/pseudo/lexer.py
index f8952470..3f666c4b 100644
--- a/src/soc/decoder/pseudo/lexer.py
+++ b/src/soc/decoder/pseudo/lexer.py
@@ -240,6 +240,7 @@ class PowerLexer:
         'RBRACK',
         'COLON',
         'EQ',
+        'ASSIGNEA',
         'ASSIGN',
         'LTU',
         'GTU',
@@ -291,6 +292,7 @@ class PowerLexer:
 
     t_COLON = r':'
     t_EQ = r'='
+    t_ASSIGNEA = r'<-iea'
     t_ASSIGN = r'<-'
     t_LTU = r'<u'
     t_GTU = r'>u'
diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 8613d2a4..bd05b4e9 100644
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -23,7 +23,7 @@ import ast
 # Helper function
 
 
-def Assign(left, right):
+def Assign(left, right, iea_mode):
     names = []
     print("Assign", left, right)
     if isinstance(left, ast.Name):
@@ -320,7 +320,8 @@ class PowerParser:
     # augassign: ('+=' | '-=' | '*=' | '/=' | '%=' | '&=' | '|=' | '^=' |
     #             '<<=' | '>>=' | '**=' | '//=')
     def p_expr_stmt(self, p):
-        """expr_stmt : testlist ASSIGN testlist
+        """expr_stmt : testlist ASSIGNEA testlist
+                     | testlist ASSIGN testlist
                      | testlist """
         print("expr_stmt", p)
         if len(p) == 2:
@@ -328,6 +329,7 @@ class PowerParser:
             #p[0] = ast.Discard(p[1])
             p[0] = p[1]
         else:
+            iea_mode = p[2] == '<-iea'
             name = None
             if isinstance(p[1], ast.Name):
                 name = p[1].id
@@ -356,7 +358,7 @@ class PowerParser:
             print("expr assign", name, p[1])
             if name and name in self.gprs:
                 self.write_regs.add(name)  # add to list of regs to write
-            p[0] = Assign(p[1], p[3])
+            p[0] = Assign(p[1], p[3], iea_mode)
 
     def p_flow_stmt(self, p):
         "flow_stmt : return_stmt"