From: lkcl Date: Tue, 21 Jun 2022 19:39:56 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1618 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab0dc649508d20ad2c72848ca5489967e0200fac;p=libreriscv.git --- diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 4af881682..d73470cf3 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -497,14 +497,11 @@ When Rc=1 a corresponding Vector of co-resultant CRs is also created. No special action is taken: the result and its CR Field are stored "as usual" exactly as all other SVP64 Rc=1 operations. -Implementors must keep in mind that Parallel Reduction is an abstracted -concept of a "Schedule" that issues Scalar Operations. It is -**not permitted** to assume that the accuracy can be made higher than that -of performing the exact same Scalar instructions just because a Parallel -Reduction Schedule is being used. - -Also note that the Schedule only makes sense on top of certain instructions: -X-Form with a Register Profile of `RT,RA,RB` is fine. +Note that the Schedule only makes sense on top of certain instructions: +X-Form with a Register Profile of `RT,RA,RB` is fine. Like Scalar +Reduction, nothing is prohibited: +the results of execution on an unsuitable instruction may simply +not make sense. # Fail-on-first