From: lkcl <lkcl@web>
Date: Sun, 20 Dec 2020 16:51:58 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1127
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab10b8a94bf8cecf129825c6084d603e45428e07;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 87be35365..fa64a93ac 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -297,7 +297,7 @@ registers have access to the same 32 registers.
 | 110       | Vector | `r2-r126` | `RA 0b10`      |
 | 111       | Vector | `r3-r127` | `RA 0b11`      |
 
-# EXTRA2
+## EXTRA2
 
 alternative which is understandable and, if EXTRA2 is zero will map to
 "no effect" i.e Scalar OpenPOWER register naming: