From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jun 2018 02:55:11 +0000 (+0100)
Subject: add example code
X-Git-Tag: convert-csv-opcode-to-binary~5275
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab1427f0919bdae2beda2ea11ffa25f6545db233;p=libreriscv.git

add example code
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 0d4f43c3d..e3a951273 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -667,8 +667,8 @@ loop:
 
  \begin{itemize}
    \item Actually about parallelism, not Vectors (or SIMD) per se
-   \item Only actually needs 3 actual instructions plus CSRs\\
-         (RVV - and "standard" SIMD - require ISA duplication)
+   \item Only needs 3 actual instructions (plus CSRs)\\
+         RVV - and "standard" SIMD - require ISA duplication
    \item Designed for flexibility (graded levels of complexity)
    \item Huge range of implementor freedom
    \item Fits RISC-V ethos: achieve more with less