From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 10 Aug 2019 00:35:13 +0000 (-0700)
Subject: Check nusers of DSP output, not whole flop
X-Git-Tag: working-ls180~1039^2~245
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab1d63a56595f11e10a5326bd83ce84d08badabe;p=yosys.git

Check nusers of DSP output, not whole flop
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index f982a10cf..5dee36a11 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -112,8 +112,8 @@ endcode
 match ffP
 	if param(dsp, \PREG).as_int() == 0
 	if !sigPused.empty()
+	if nusers(sigPused) == 2
 	select ffP->type.in($dff)
-	index <int> nusers(port(ffP, \D)) === 2
 	// DSP48E1 does not support clock inversion
 	select param(ffP, \CLK_POLARITY).as_bool()
 	filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)