From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 24 Nov 2015 11:16:19 +0000 (+0100)
Subject: Added PRIM_DLATCHRS support to verific front-end
X-Git-Tag: yosys-0.6~59^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab2d8e5c8cc78eb60f380fbdf5b09f2401ce27f6;p=yosys.git

Added PRIM_DLATCHRS support to verific front-end
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index e40f24cb0..45cd4f3fc 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -314,6 +314,16 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
 		return true;
 	}
 
+	if (inst->Type() == PRIM_DLATCHRS)
+	{
+		if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
+			module->addDlatch(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
+		else
+			module->addDlatchsr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetSet()), net_map.at(inst->GetReset()),
+					net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
+		return true;
+	}
+
 	#define IN  operatorInput(inst, net_map)
 	#define IN1 operatorInput1(inst, net_map)
 	#define IN2 operatorInput2(inst, net_map)