From: Tiago Mück Date: Thu, 28 May 2020 21:16:20 +0000 (-0500) Subject: mem-ruby: Sequencer can be used without cache X-Git-Tag: develop-gem5-snapshot~645 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab309b9e4e4fa1f2a0b985e9c9e5d5925592db3b;hp=aa8bca47f416a226cda146112f5a59398e698f8f;p=gem5.git mem-ruby: Sequencer can be used without cache Moved the dcache check to the LLSC functions that use it. This allows a Sequencer to be coupled with a gem5 object that does not need a cache (as long as it doesn't issue LLSC instructions). Also, icache was not used at all so it was removed. Change-Id: I04bd2711f8d0a7dfc952cff8e0020d2d1881cae1 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31267 Reviewed-by: Jason Lowe-Power Reviewed-by: Bradford Beckmann Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/configs/learning_gem5/part3/msi_caches.py b/configs/learning_gem5/part3/msi_caches.py index f8994265c..d718a6bef 100644 --- a/configs/learning_gem5/part3/msi_caches.py +++ b/configs/learning_gem5/part3/msi_caches.py @@ -82,7 +82,6 @@ class MyCacheSystem(RubySystem): # and other controllers, too. self.sequencers = [RubySequencer(version = i, # I/D cache is combined and grab from ctrl - icache = self.controllers[i].cacheMemory, dcache = self.controllers[i].cacheMemory, clk_domain = self.controllers[i].clk_domain, ) for i in range(len(cpus))] diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py b/configs/learning_gem5/part3/ruby_caches_MI_example.py index 29b66a6d4..8c0e563e9 100644 --- a/configs/learning_gem5/part3/ruby_caches_MI_example.py +++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py @@ -82,7 +82,6 @@ class MyCacheSystem(RubySystem): # and other controllers, too. self.sequencers = [RubySequencer(version = i, # I/D cache is combined and grab from ctrl - icache = self.controllers[i].cacheMemory, dcache = self.controllers[i].cacheMemory, clk_domain = self.controllers[i].clk_domain, ) for i in range(len(cpus))] diff --git a/configs/learning_gem5/part3/test_caches.py b/configs/learning_gem5/part3/test_caches.py index 855bf17b9..cdf5d1952 100644 --- a/configs/learning_gem5/part3/test_caches.py +++ b/configs/learning_gem5/part3/test_caches.py @@ -76,7 +76,6 @@ class TestCacheSystem(RubySystem): self.sequencers = [RubySequencer(version = i, # I/D cache is combined and grab from ctrl - icache = self.controllers[i].cacheMemory, dcache = self.controllers[i].cacheMemory, clk_domain = self.clk_domain, ) for i in range(num_testers)] diff --git a/configs/ruby/AMD_Base_Constructor.py b/configs/ruby/AMD_Base_Constructor.py index a347f4373..6f13c1e0f 100644 --- a/configs/ruby/AMD_Base_Constructor.py +++ b/configs/ruby/AMD_Base_Constructor.py @@ -78,7 +78,6 @@ class CPCntrl(AMD_Base_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -86,7 +85,6 @@ class CPCntrl(AMD_Base_Controller, CntrlBase): self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() - self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py index 58711ea0d..6705fc1a7 100644 --- a/configs/ruby/GPU_RfO.py +++ b/configs/ruby/GPU_RfO.py @@ -118,7 +118,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -126,7 +125,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() - self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 @@ -180,7 +178,6 @@ class TCPCntrl(TCP_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.is_cpu_sequencer = True @@ -209,7 +206,6 @@ class TCPCntrl(TCP_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.is_cpu_sequencer = True @@ -243,7 +239,6 @@ class SQCCntrl(SQC_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.support_data_reqs = False @@ -268,7 +263,6 @@ class SQCCntrl(SQC_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.support_data_reqs = False diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py index 6a6dec53b..3ea2998eb 100644 --- a/configs/ruby/GPU_VIPER.py +++ b/configs/ruby/GPU_VIPER.py @@ -105,7 +105,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -113,7 +112,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() - self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 @@ -166,7 +164,6 @@ class TCPCntrl(TCP_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.is_cpu_sequencer = True @@ -197,7 +194,6 @@ class TCPCntrl(TCP_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.is_cpu_sequencer = True @@ -232,7 +228,6 @@ class SQCCntrl(SQC_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.support_data_reqs = False diff --git a/configs/ruby/GPU_VIPER_Baseline.py b/configs/ruby/GPU_VIPER_Baseline.py index 5a32222fc..a55ecd413 100644 --- a/configs/ruby/GPU_VIPER_Baseline.py +++ b/configs/ruby/GPU_VIPER_Baseline.py @@ -104,7 +104,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -112,7 +111,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() - self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 @@ -165,7 +163,6 @@ class TCPCntrl(TCP_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.is_cpu_sequencer = True @@ -196,7 +193,6 @@ class SQCCntrl(SQC_Controller, CntrlBase): self.L1cache.resourceStalls = False self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.support_data_reqs = False diff --git a/configs/ruby/GPU_VIPER_Region.py b/configs/ruby/GPU_VIPER_Region.py index fa431e3d1..1d63cb0e4 100644 --- a/configs/ruby/GPU_VIPER_Region.py +++ b/configs/ruby/GPU_VIPER_Region.py @@ -105,7 +105,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -113,7 +112,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() - self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 @@ -166,7 +164,6 @@ class TCPCntrl(TCP_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.is_cpu_sequencer = True @@ -197,7 +194,6 @@ class SQCCntrl(SQC_Controller, CntrlBase): self.L1cache.resourceStalls = False self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1cache self.sequencer.dcache = self.L1cache self.sequencer.ruby_system = ruby_system self.sequencer.support_data_reqs = False diff --git a/configs/ruby/Garnet_standalone.py b/configs/ruby/Garnet_standalone.py index 4b7ca8d12..13e990d15 100644 --- a/configs/ruby/Garnet_standalone.py +++ b/configs/ruby/Garnet_standalone.py @@ -79,8 +79,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, cacheMemory = cache, ruby_system = ruby_system) - cpu_seq = RubySequencer(icache = cache, - dcache = cache, + cpu_seq = RubySequencer(dcache = cache, garnet_standalone = True, ruby_system = ruby_system) diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py index 7cfb83242..91ccb5896 100644 --- a/configs/ruby/MESI_Three_Level.py +++ b/configs/ruby/MESI_Three_Level.py @@ -141,7 +141,6 @@ def create_system(options, full_system, system, dma_ports, bootmem, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j, - icache = l0i_cache, clk_domain = clk_domain, dcache = l0d_cache, ruby_system = ruby_system) diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py index 77fef767f..96650e010 100644 --- a/configs/ruby/MESI_Two_Level.py +++ b/configs/ruby/MESI_Two_Level.py @@ -102,7 +102,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, transitions_per_cycle = options.ports, enable_prefetch = False) - cpu_seq = RubySequencer(version = i, icache = l1i_cache, + cpu_seq = RubySequencer(version = i, dcache = l1d_cache, clk_domain = clk_domain, ruby_system = ruby_system) diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 264f709ec..6e5c8b4e2 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -92,7 +92,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, clk_domain=clk_domain, ruby_system=ruby_system) - cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache, + cpu_seq = RubySequencer(version=i, dcache=cache, clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py index 91ff4d232..eb008ea58 100644 --- a/configs/ruby/MOESI_AMD_Base.py +++ b/configs/ruby/MOESI_AMD_Base.py @@ -101,7 +101,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer = RubySequencer() self.sequencer.version = self.seqCount() - self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache self.sequencer.ruby_system = ruby_system self.sequencer.coreid = 0 @@ -109,7 +108,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer1 = RubySequencer() self.sequencer1.version = self.seqCount() - self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py index a78f73c68..5366fe7ab 100644 --- a/configs/ruby/MOESI_CMP_directory.py +++ b/configs/ruby/MOESI_CMP_directory.py @@ -113,7 +113,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, clk_domain=clk_domain, ruby_system=ruby_system) - cpu_seq = RubySequencer(version=i, icache=l1i_cache, + cpu_seq = RubySequencer(version=i, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system) diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py index 80944f566..28ec52f3d 100644 --- a/configs/ruby/MOESI_CMP_token.py +++ b/configs/ruby/MOESI_CMP_token.py @@ -117,7 +117,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, clk_domain=clk_domain, ruby_system=ruby_system) - cpu_seq = RubySequencer(version=i, icache=l1i_cache, + cpu_seq = RubySequencer(version=i, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system) diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py index c83bb72dc..1e00f0f47 100644 --- a/configs/ruby/MOESI_hammer.py +++ b/configs/ruby/MOESI_hammer.py @@ -109,7 +109,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, clk_domain=clk_domain, ruby_system=ruby_system) - cpu_seq = RubySequencer(version=i, icache=l1i_cache, + cpu_seq = RubySequencer(version=i, dcache=l1d_cache,clk_domain=clk_domain, ruby_system=ruby_system) diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index dbc85c418..0614c1108 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -73,7 +73,6 @@ Sequencer::Sequencer(const Params *p) { m_outstanding_count = 0; - m_instCache_ptr = p->icache; m_dataCache_ptr = p->dcache; m_max_outstanding_requests = p->max_outstanding_requests; m_deadlock_threshold = p->deadlock_threshold; @@ -81,8 +80,6 @@ Sequencer::Sequencer(const Params *p) m_coreId = p->coreid; // for tracking the two CorePair sequencers assert(m_max_outstanding_requests > 0); assert(m_deadlock_threshold > 0); - assert(m_instCache_ptr != NULL); - assert(m_dataCache_ptr != NULL); m_runningGarnetStandalone = p->garnet_standalone; } @@ -94,6 +91,8 @@ Sequencer::~Sequencer() void Sequencer::llscLoadLinked(const Addr claddr) { + fatal_if(m_dataCache_ptr == NULL, + "%s must have a dcache object to support LLSC requests.", name()); AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr); if (line) { line->setLocked(m_version); @@ -105,6 +104,9 @@ Sequencer::llscLoadLinked(const Addr claddr) void Sequencer::llscClearMonitor(const Addr claddr) { + // clear monitor is called for all stores and evictions + if (m_dataCache_ptr == NULL) + return; AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr); if (line && line->isLocked(m_version)) { line->clearLocked(); @@ -116,6 +118,8 @@ Sequencer::llscClearMonitor(const Addr claddr) bool Sequencer::llscStoreConditional(const Addr claddr) { + fatal_if(m_dataCache_ptr == NULL, + "%s must have a dcache object to support LLSC requests.", name()); AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr); if (!line) return false; @@ -137,6 +141,7 @@ Sequencer::llscStoreConditional(const Addr claddr) bool Sequencer::llscCheckMonitor(const Addr address) { + assert(m_dataCache_ptr != NULL); const Addr claddr = makeLineAddress(address); AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr); if (!line) diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 92fdab690..4a5e28123 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -212,7 +212,6 @@ class Sequencer : public RubyPort int m_max_outstanding_requests; CacheMemory* m_dataCache_ptr; - CacheMemory* m_instCache_ptr; // The cache access latency for top-level caches (L0/L1). These are // currently assessed at the beginning of each memory access through the diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 0a28d3631..0acd87a4b 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -1,3 +1,15 @@ +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2009 Advanced Micro Devices, Inc. # Copyright (c) 2020 ARM Limited # All rights reserved. @@ -76,7 +88,6 @@ class RubySequencer(RubyPort): cxx_class = 'Sequencer' cxx_header = "mem/ruby/system/Sequencer.hh" - icache = Param.RubyCache("") dcache = Param.RubyCache("") max_outstanding_requests = Param.Int(16,