From: Cesar Strauss <cestrauss@gmail.com>
Date: Tue, 28 Dec 2021 21:06:02 +0000 (-0300)
Subject: Add an --inorder option to test_issuer.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab38260fedb13b7b83cf2dbec6aa2ce44e8e3e88;p=soc.git

Add an --inorder option to test_issuer.py

To use, add "--inorder" as the last option, before the test list
It's using the newly added pspec flag (see openpower-isa repo)
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 732cfcf7..13846160 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1517,9 +1517,6 @@ class TestIssuerInternal(TestIssuerBase):
 class TestIssuer(Elaboratable):
     def __init__(self, pspec):
         self.ti = TestIssuerInternal(pspec)
-        # XXX TODO: make this a command-line selectable option from pspec
-        #from soc.simple.inorder import TestIssuerInternalInOrder
-        #self.ti = TestIssuerInternalInOrder(pspec)
         self.pll = DummyPLL(instance=True)
 
         self.dbg_rst_i = Signal(reset_less=True)
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 5d22ca09..b5799ecf 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -46,6 +46,12 @@ if __name__ == "__main__":
         allow_overlap = True
         del sys.argv[1]
 
+    # use in-order issuer, instead of the original FSM based one
+    inorder = False
+    if len(sys.argv) >= 2 and sys.argv[1] == '--inorder':
+        inorder = True
+        del sys.argv[1]
+
     # allow list of testing to be selected by command-line
     testing = []
     for i in reversed(range(1, len(sys.argv))):
@@ -58,7 +64,7 @@ if __name__ == "__main__":
                    'branch', 'div', 'mul', 'hazard']
 
     print("SVP64 test mode enabled", svp64, "overlap",
-          allow_overlap, "testing", testing)
+          allow_overlap, "in-order", inorder, "testing", testing)
 
     unittest.main(exit=False)
     suite = unittest.TestSuite()
@@ -83,7 +89,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, svp64=svp64,
+            suite.addTest(TestRunner(data, svp64=svp64, inorder=inorder,
                                      allow_overlap=allow_overlap))
 
     runner = unittest.TextTestRunner()
diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 2daa86a5..b4458c0c 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -19,6 +19,7 @@ from openpower.decoder.isa.all import ISA
 from openpower.endian import bigendian
 
 from soc.simple.issuer import TestIssuerInternal
+from soc.simple.inorder import TestIssuerInternalInOrder
 
 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
                                        wait_for_busy_clear,
@@ -178,7 +179,10 @@ class HDLRunner(StateRunner):
         self.svstate_i = Signal(64)
 
         #hard_reset = Signal(reset_less=True)
-        self.issuer = TestIssuerInternal(pspec)
+        if pspec.inorder:
+            self.issuer = TestIssuerInternalInOrder(pspec)
+        else:
+            self.issuer = TestIssuerInternal(pspec)
         # use DMI RESET command instead, this does actually work though
         # issuer = ResetInserter({'coresync': hard_reset,
         #                        'sync': hard_reset})(issuer)
@@ -384,11 +388,11 @@ class HDLRunner(StateRunner):
 
 class TestRunner(TestRunnerBase):
     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
-                 svp64=True, run_hdl=True, run_sim=True,
+                 svp64=True, inorder=False, run_hdl=True, run_sim=True,
                  allow_overlap=False):
         if run_hdl:
             run_hdl = HDLRunner
         super().__init__(tst_data, microwatt_mmu=microwatt_mmu,
-                         rom=rom,
+                         rom=rom, inorder=inorder,
                          svp64=svp64, run_hdl=run_hdl, run_sim=run_sim,
                          allow_overlap=allow_overlap)