From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 14 Sep 2020 08:55:49 +0000 (+0100)
Subject: mem: Replace any getDTBPtr/getITBPtr usage
X-Git-Tag: develop-gem5-snapshot~563
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab474613bc5f8191c7bca298334aa6567fc3bc7d;p=gem5.git

mem: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I0759baec87b3682a057239a6b3b8f79fe3f5592c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34983
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/mem/translating_port_proxy.cc b/src/mem/translating_port_proxy.cc
index 1e8d83650..27a2d67c6 100644
--- a/src/mem/translating_port_proxy.cc
+++ b/src/mem/translating_port_proxy.cc
@@ -45,6 +45,7 @@
 
 #include "mem/translating_port_proxy.hh"
 
+#include "arch/generic/mmu.hh"
 #include "base/chunk_generator.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
@@ -61,10 +62,9 @@ TranslatingPortProxy::TranslatingPortProxy(
 bool
 TranslatingPortProxy::tryTLBsOnce(RequestPtr req, BaseTLB::Mode mode) const
 {
-    BaseTLB *dtb = _tc->getDTBPtr();
-    BaseTLB *itb = _tc->getDTBPtr();
-    return dtb->translateFunctional(req, _tc, mode) == NoFault ||
-           itb->translateFunctional(req, _tc, BaseTLB::Read) == NoFault;
+    BaseMMU *mmu = _tc->getMMUPtr();
+    return mmu->translateFunctional(req, _tc, mode) == NoFault ||
+           mmu->translateFunctional(req, _tc, BaseTLB::Execute) == NoFault;
 }
 
 bool