From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Nov 2021 14:32:21 +0000 (+0000)
Subject: code-comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab4bc5b50378842cf8f33ec9ea7821ab850525a0;p=soc.git

code-comments
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 652f5987..bd770a94 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -672,7 +672,8 @@ class NonProductionCore(ControlBase):
         # the detection of what shall be written to is based
         # on *issue*.  it is delayed by 1 cycle so that instructions
         # "addi 5,5,0x2" do not cause combinatorial loops due to
-        # fake-dependency on *themselves*
+        # fake-dependency on *themselves*.  this will totally fail
+        # spectacularly when doing multi-issue
         print ("write vector (for regread)", regfile, wvset)
         wviaddr_en = Signal(len(wvset), name="wv_issue_addr_en_"+name)
         issue_active = Signal(name="iactive_"+name)