From: Luke Kenneth Casson Leighton Date: Mon, 28 Sep 2020 11:33:33 +0000 (+0100) Subject: lots of sorting out iopads X-Git-Tag: 24jan2021_ls180~294 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab4d1fa021ca35ee49deea4903593a20d5cc7ec1;p=soc.git lots of sorting out iopads * add sdram clock * rename serial to uart * disable I2C for now (needs bi-directional pads) * make sdram and sd0 "en" only one pin (sort out litex issue) * add "NC" pins so that there are no missing pins --- diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py index e920b1ac..e6da82b1 100644 --- a/src/soc/debug/jtag.py +++ b/src/soc/debug/jtag.py @@ -24,7 +24,7 @@ class Pins: gpios = [] for i in range(16): gpios.append("gpio%d*" % i) - self.io_names = {'serial': ['tx+', 'rx-'], 'gpio': gpios} + self.io_names = {'uart': ['tx+', 'rx-'], 'gpio': gpios} def __iter__(self): # start parsing io_names and enumerate them to return pin specs @@ -45,7 +45,8 @@ class JTAG(DMITAP, Pins): # enumerate pin specs and create IOConn Records. self.ios = [] # these are enumerated in external_ports for fn, pin, iotype, pin_name in list(self): - self.ios.append(self.add_io(iotype=iotype, name=pin_name)) + io = self.add_io(iotype=iotype, name=pin_name) + self.ios.append(io) # this is redundant. or maybe part of testing, i don't know. self.sr = self.add_shiftreg(ircode=4, length=3) diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index c5a6cbd1..9cc7d893 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -36,8 +36,8 @@ def make_wb_slave(prefix, obj): def make_pad(res, dirn, name, suffix, cpup, iop): cpud, iod = ('i', 'o') if dirn else ('o', 'i') - res['%s_%s__%s' % (cpud, name, suffix)] = cpup - res['%s_%s__%s' % (iod, name, suffix)] = iop + res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup + res['%s_%s__pad__%s' % (iod, name, suffix)] = iop def make_jtag_ioconn(res, pin, cpupads, iopads): @@ -207,15 +207,15 @@ class LibreSoC(CPU): if variant == 'ls180': # urr yuk. have to expose iopads / pins from core to litex # then back again. cut _some_ of that out by connecting - self.cpuresources = (make_uart('serial', 0), + self.cpuresources = (make_uart('uart', 0), make_gpio('gpio', 0, 16)) - self.padresources = (make_uart('serial', 0), + self.padresources = (make_uart('uart', 0), make_gpio('gpio', 0, 16)) self.cpu_cm = ConstraintManager(self.cpuresources, []) self.pad_cm = ConstraintManager(self.cpuresources, []) - self.cpupads = {'serial': self.cpu_cm.request('serial', 0), + self.cpupads = {'uart': self.cpu_cm.request('uart', 0), 'gpio': self.cpu_cm.request('gpio', 0)} - self.iopads = {'serial': self.pad_cm.request('serial', 0), + self.iopads = {'uart': self.pad_cm.request('uart', 0), 'gpio': self.pad_cm.request('gpio', 0)} p = Pins() diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index 8aa713e5..49f32b3d 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -73,7 +73,7 @@ _io = [ Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")), Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), - Subsignal("data_oe", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), + Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")), Misc("SLEWRATE=FAST"), IOStandard("LVCMOS33"), ), @@ -90,9 +90,7 @@ _io = [ Subsignal("dq_o", Pins( "J16 L18 M18 N18 P18 T18 T17 U20", "E19 D20 D19 C20 E18 F18 J18 J17")), - Subsignal("dq_oe", Pins( - "J16 L18 M18 N18 P18 T18 T17 U20", - "E19 D20 D19 C20 E18 F18 J18 J17")), + Subsignal("dq_oe", Pins("J17")), Subsignal("we_n", Pins("T20")), Subsignal("ras_n", Pins("R20")), Subsignal("cas_n", Pins("T19")), @@ -115,13 +113,17 @@ n_gpio = 16 _io.append( make_gpio("gpio", 0, n_gpio) ) # EINT: 3 pins -_io.append( ("eint", 3, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) ) +_io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) ) # UART0: 2 pins _io.append(make_uart("uart", 0)) # UART1: 2 pins _io.append(make_uart("uart", 1)) +# not connected - eurgh have to adjust this to match the total pincount. +num_nc = 43 +nc = ' '.join("NC%d" % i for i in range(num_nc)) +_io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33"))) # Platform ----------------------------------------------------------------------------------------- diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 9c7547f7..25da0a33 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -90,9 +90,9 @@ class SDRPad(Module): _o = getattr(pad, "%s_o" % name) _oe = getattr(pad, "%s_oe" % name) _i = getattr(pad, "%s_i" % name) + self.specials += SDROutput(clk=clk, i=oe, o=_oe) for j in range(len(_o)): self.specials += SDROutput(clk=clk, i=o[j], o=_o[j]) - self.specials += SDROutput(clk=clk, i=oe, o=_oe[j]) self.specials += SDRInput(clk=clk, i=_i[j], o=i[j]) @@ -220,11 +220,15 @@ class GENSDRPHY(Module): # DQ/DM Data Path ------------------------------------------------- d = dfi.p0 + wren = [] self.submodules.dq = SDRPad(pads, "dq", d.wrdata, d.wrdata_en, d.rddata) if hasattr(pads, "dm"): + # optimisation by yosys, fudge it... sigh + dm = Signal(len(pads.dm)) for i in range(len(pads.dm)): - self.comb += pads.dm[i].eq(0) # FIXME + self.comb += dm[i].eq(1) + self.sync += pads.dm[i].eq(dm[i]) # FIXME # DQ/DM Control Path ---------------------------------------------- rddata_en = Signal(cl + cmd_latency) @@ -362,8 +366,14 @@ class LibreSoCSim(SoCCore): self.add_constant("MEMTEST_ADDR_DEBUG", 1) self.add_constant("MEMTEST_DATA_DEBUG", 1) + # SDRAM clock + sys_clk = ClockSignal() + sdr_clk = platform.request("sdram_clock") + #self.specials += DDROutput(1, 0, , sdram_clk) + self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk) + # UART - uart_core_pads = self.cpu.cpupads['serial'] + uart_core_pads = self.cpu.cpupads['uart'] self.submodules.uart_phy = uart.UARTPHY( pads = uart_core_pads, clk_freq = self.sys_clk_freq, @@ -373,7 +383,7 @@ class LibreSoCSim(SoCCore): rx_fifo_depth = 16)) # "real" pads connect to C4M JTAG iopad uart_pads = platform.request(uart_name) # "real" (actual) pin - uart_io_pads = self.cpu.iopads['serial'] # C4M JTAG pads + uart_io_pads = self.cpu.iopads['uart'] # C4M JTAG pads self.comb += uart_pads.tx.eq(uart_io_pads.tx) self.comb += uart_io_pads.rx.eq(uart_pads.rx) @@ -386,11 +396,11 @@ class LibreSoCSim(SoCCore): self.submodules.gpio = GPIOTristateASIC(gpio_core_pads) self.add_csr("gpio") - gpio_pads = platform.request("gpio") + gpio_pads = platform.request("gpio") # "real" (actual) pins gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads - self.comb += gpio_pads.i.eq(gpio_io_pads.i) - self.comb += gpio_io_pads.o.eq(gpio_pads.o) - self.comb += gpio_io_pads.oe.eq(gpio_pads.oe) + self.comb += gpio_io_pads.i.eq(gpio_pads.i) + self.comb += gpio_pads.o.eq(gpio_io_pads.o) + self.comb += gpio_pads.oe.eq(gpio_io_pads.oe) # SPI Master self.submodules.spi_master = SPIMaster( @@ -411,15 +421,26 @@ class LibreSoCSim(SoCCore): self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi) self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo) + # NC - allows some iopads to be connected up + # sigh, just do something, anything, to stop yosys optimising these out + nc_pads = platform.request("nc") + num_nc = len(nc_pads) + self.nc = Signal(num_nc) + self.comb += self.nc.eq(nc_pads) + self.dummy = Signal(num_nc) + for i in range(num_nc): + self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0]) + # PWM for i in range(2): name = "pwm%d" % i setattr(self.submodules, name, PWM(platform.request("pwm", i))) self.add_csr(name) - # I2C Master - self.submodules.i2c = I2CMaster(platform.request("i2c")) - self.add_csr("i2c") + if False: # TODO: convert to _i _o _oe + # I2C Master + self.submodules.i2c = I2CMaster(platform.request("i2c")) + self.add_csr("i2c") # SDCard -----------------------------------------------------