From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 17:26:07 +0000 (+0100) Subject: hmmm sync-delay wport write and wen X-Git-Tag: div_pipeline~594 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab51b5feb117c8d9bc1a512c5e669b0ebd06a16e;p=soc.git hmmm sync-delay wport write and wen --- diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index aa63d6d9..c1bbf743 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -163,7 +163,7 @@ class NonProductionCore(Elaboratable): # only if one FU actually requests (and is granted) the port # will the write-enable be activated with m.If(wrpick.en_o): - comb += wport.wen.eq(write) + sync += wport.wen.eq(write) # connect up the FU req/go signals and the reg-read to the FU # these are arbitrated by Data.ok signals @@ -187,7 +187,7 @@ class NonProductionCore(Elaboratable): wsigs.append(dest) # here is where we create the Write Broadcast Bus. simple, eh? - comb += wport.data_i.eq(ortreereduce(wsigs, "data")) + sync += wport.data_i.eq(ortreereduce(wsigs, "data")) return m