From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Mon, 30 Sep 2019 02:56:09 +0000 (+1000)
Subject: fpga: Arty A7's don't need multiple filesets
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab5c6ab9ac98ff18dc27d9e5a71b5d08a513b602;p=microwatt.git

fpga: Arty A7's don't need multiple filesets

the XDC is identical between variants, so is the fileset

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

diff --git a/fpga/arty_a7-35.xdc b/fpga/arty_a7-35.xdc
deleted file mode 100644
index 481d8e4..0000000
--- a/fpga/arty_a7-35.xdc
+++ /dev/null
@@ -1,10 +0,0 @@
-set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
-
-set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
-
-set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
-set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];
-
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property CFGBVS VCCO [current_design]
diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc
new file mode 100644
index 0000000..481d8e4
--- /dev/null
+++ b/fpga/arty_a7.xdc
@@ -0,0 +1,10 @@
+set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
+
+set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
+
+set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
+set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
diff --git a/microwatt.core b/microwatt.core
index 9604cee..f815c15 100644
--- a/microwatt.core
+++ b/microwatt.core
@@ -68,14 +68,9 @@ filesets:
       - fpga/nexys-video.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
-  arty_a7-35:
-    files:
-      - fpga/arty_a7-35.xdc : {file_type : xdc}
-      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
-
-  arty_a7-100:
+  arty_a7:
     files:
-      - fpga/arty_a7-35.xdc : {file_type : xdc}
+      - fpga/arty_a7.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
   cmod_a7-35:
@@ -102,7 +97,7 @@ targets:
 
   arty_a7-35:
     default_tool: vivado
-    filesets: [core, arty_a7-35, soc, fpga, debug_xilinx]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
@@ -110,7 +105,7 @@ targets:
 
   arty_a7-100:
     default_tool: vivado
-    filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a100ticsg324-1L}