From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 15:43:58 +0000 (-0700)
Subject: Add testcase from #335, fixed by #1130
X-Git-Tag: yosys-0.9~45
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7;p=yosys.git

Add testcase from #335, fixed by #1130
---

diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v
new file mode 100644
index 000000000..f3b6e5dfe
--- /dev/null
+++ b/tests/memories/issue00335.v
@@ -0,0 +1,28 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module ram2 (input clk,
+             input             sel,
+             input             we, 
+             input [SIZE-1:0]  adr, 
+             input [63:0]      dat_i, 
+             output reg [63:0] dat_o);
+   parameter  SIZE = 5; // Address size
+
+   reg [63:0] mem [0:(1 << SIZE)-1];
+   integer    i;
+
+   initial begin
+      for (i = 0; i < (1<<SIZE) - 1; i = i + 1)
+        mem[i] <= 0;
+   end
+   
+   always @(posedge clk)
+     if (sel) begin
+       if (~we)
+         dat_o <= mem[adr];
+       else
+         mem[adr] <= dat_i;
+     end
+endmodule