From: whitequark <whitequark@whitequark.org>
Date: Sun, 7 Mar 2021 14:29:30 +0000 (+0000)
Subject: cxxrtl: don't assert on edge sync rules tied to a constant.
X-Git-Tag: yosys-0.10~258^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab76d9cec5ba38539f1578a78f3c810a659ea092;p=yosys.git

cxxrtl: don't assert on edge sync rules tied to a constant.

These are commonly the result of tying an async reset to an inactive
level.
---

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index b6cc4bb6d..0071bda7f 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1518,6 +1518,8 @@ struct CxxrtlWorker {
 			if (!sync->signal.empty()) {
 				sync_bit = sync->signal[0];
 				sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
+				if (!sync_bit.is_wire())
+					continue; // a clock, or more commonly a reset, can be tied to a constant driver
 			}
 
 			pool<std::string> events;
@@ -2285,6 +2287,8 @@ struct CxxrtlWorker {
 	void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
 	{
 		signal = sigmap(signal);
+		if (signal.is_fully_const())
+			return; // a clock, or more commonly a reset, can be tied to a constant driver
 		log_assert(is_valid_clock(signal));
 		log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);