From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 18:13:49 +0000 (-0700)
Subject: Add simcells.v, simlib.v, and some output
X-Git-Tag: yosys-0.9~30^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab7c4319058bbae8758cda9f246c92c324dfafbf;p=yosys.git

Add simcells.v, simlib.v, and some output
---

diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index fc4175be8..5292d1615 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -4,5 +4,15 @@ set -e
 
 echo "Running syntax check on arch sim models"
 for arch in ../../techlibs/*; do
-	find $arch -name cells_sim.v -print0 | xargs -0 -n1 -r iverilog -t null -I$arch
+	find $arch -name cells_sim.v | while read path; do
+		echo -n "Test $path ->"
+		iverilog -t null -I$arch $path
+		echo " ok"
+	done
+done
+
+for path in "../../techlibs/common/simcells.v"  "../../techlibs/common/simlib.v"; do
+	echo -n "Test $path ->"
+	iverilog -t null $path
+	echo " ok"
 done