From: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Fri, 2 Jun 2017 14:21:55 +0000 (+0000)
Subject: rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vector... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab82e126e749c99f77a0fa7230ee104fe47660d9;p=gcc.git

rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vector absolute builtins.

[gcc]

2017-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling
	for early expansion of vector absolute builtins.

[gcc/testsuite]

2017-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-abs-char.c: New.
	* gcc.target/powerpc/fold-vec-abs-floatdouble.c: New.
	* gcc.target/powerpc/fold-vec-abs-int.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong.c: New.
	* gcc.target/powerpc/fold-vec-abs-short.c: New.
	* gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: New.
	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.c: New.
	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c: New.
	* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: New.

From-SVN: r248830
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4f861e16ade..7c75984ddce 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-02  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling
+	for early expansion of vector absolute builtins.
+
 2017-06-02  Richard Biener  <rguenther@suse.de>
 
 	* tree-vect-slp.c (vect_detect_hybrid_slp_2): Match up
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fcdb8ac9128..96bd6e069c3 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -17329,6 +17329,24 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
 	gsi_replace (gsi, g, true);
 	return true;
       }
+    /* flavors of vec_abs.  */
+    case ALTIVEC_BUILTIN_ABS_V16QI:
+    case ALTIVEC_BUILTIN_ABS_V8HI:
+    case ALTIVEC_BUILTIN_ABS_V4SI:
+    case ALTIVEC_BUILTIN_ABS_V4SF:
+    case P8V_BUILTIN_ABS_V2DI:
+    case VSX_BUILTIN_XVABSDP:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
+	    && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
+	      return false;
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, ABS_EXPR, arg0);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
     default:
       break;
     }
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7bb506bc240..611a851a99b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2017-06-02  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/fold-vec-abs-char.c: New.
+	* gcc.target/powerpc/fold-vec-abs-floatdouble.c: New.
+	* gcc.target/powerpc/fold-vec-abs-int.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong.c: New.
+	* gcc.target/powerpc/fold-vec-abs-short.c: New.
+	* gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: New.
+	* gcc.target/powerpc/fold-vec-abs-int-fwrapv.c: New.
+	* gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c: New.
+	* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: New.
+
 2017-06-02  Nathan Sidwell  <nathan@acm.org>
 
 	* g++.dg/pr45330.C: Adjust.  Check breadth-firstness.
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c
new file mode 100644
index 00000000000..739f06e0fe5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with char
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed char
+test2 (vector signed char x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsububm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c
new file mode 100644
index 00000000000..239c9193464
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with char
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed char
+test2 (vector signed char x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsububm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-floatdouble.c
new file mode 100644
index 00000000000..1a08618b367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-floatdouble.c
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_abs with float and
+   double inputs for VSX produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x)
+{
+  return vec_abs (x);
+}
+
+vector double
+test2 (vector double x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "xvabssp" 1 } } */
+/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
new file mode 100644
index 00000000000..34dead4e916
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
new file mode 100644
index 00000000000..77d9ca5c26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with int
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
new file mode 100644
index 00000000000..934618b91b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
new file mode 100644
index 00000000000..5b59d19346d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
new file mode 100644
index 00000000000..2562179af72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with short
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed short
+test3 (vector signed short x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuhm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
new file mode 100644
index 00000000000..d3120002b33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_abs with short
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+test3 (vector signed short x)
+{
+  return vec_abs (x);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuhm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsh" 1 } } */