From: Anton Blanchard <anton@linux.ibm.com>
Date: Wed, 20 May 2020 06:07:13 +0000 (+1000)
Subject: Exit cleanly from testbench on success
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab86b58d956512201350438097bf4e569fd91a34;p=microwatt.git

Exit cleanly from testbench on success

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/countzero_tb.vhdl b/countzero_tb.vhdl
index 21529de..42f6048 100644
--- a/countzero_tb.vhdl
+++ b/countzero_tb.vhdl
@@ -109,7 +109,6 @@ begin
             end loop;
         end loop;
 
-        assert false report "end of test" severity failure;
-        wait;
+	std.env.finish;
     end process;
 end behave;
diff --git a/dcache_tb.vhdl b/dcache_tb.vhdl
index 48c6877..1e2e07b 100644
--- a/dcache_tb.vhdl
+++ b/dcache_tb.vhdl
@@ -133,8 +133,6 @@ begin
 	wait until rising_edge(clk);
 	wait until rising_edge(clk);
 
-        assert false report "end of test" severity failure;
-        wait;
-
+	std.env.finish;
     end process;
 end;
diff --git a/divider_tb.vhdl b/divider_tb.vhdl
index 95156a3..01d1d81 100644
--- a/divider_tb.vhdl
+++ b/divider_tb.vhdl
@@ -547,7 +547,6 @@ begin
             end loop;
         end loop;
 
-        assert false report "end of test" severity failure;
-        wait;
+        std.env.finish;
     end process;
 end behave;
diff --git a/fpga/soc_reset_tb.vhdl b/fpga/soc_reset_tb.vhdl
index 26c6b1e..6c5e1b9 100644
--- a/fpga/soc_reset_tb.vhdl
+++ b/fpga/soc_reset_tb.vhdl
@@ -124,7 +124,6 @@ begin
 
 	wait for clk_period;
 
-        assert false report "end of test" severity failure;
-        wait;
+        std.env.finish;
     end process;
 end behave;
diff --git a/icache_tb.vhdl b/icache_tb.vhdl
index 09a644b..828a610 100644
--- a/icache_tb.vhdl
+++ b/icache_tb.vhdl
@@ -147,8 +147,6 @@ begin
 
         i_out.req <= '0';
 
-        assert false report "end of test" severity failure;
-        wait;
-
+        std.env.finish;
     end process;
 end;
diff --git a/multiply_tb.vhdl b/multiply_tb.vhdl
index 8f1d795..ee80de0 100644
--- a/multiply_tb.vhdl
+++ b/multiply_tb.vhdl
@@ -247,7 +247,7 @@ begin
                 report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
         end loop;
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
         wait;
     end process;
 end behave;
diff --git a/plru_tb.vhdl b/plru_tb.vhdl
index 18512e4..1afbd65 100644
--- a/plru_tb.vhdl
+++ b/plru_tb.vhdl
@@ -103,7 +103,6 @@ begin
 	wait for clk_period;
 	report "lru:" & to_hstring(lru);
 
-        assert false report "end of test" severity failure;
-        wait;
+        std.env.finish;
     end process;
 end;
diff --git a/rotator_tb.vhdl b/rotator_tb.vhdl
index 62a09ce..123058c 100644
--- a/rotator_tb.vhdl
+++ b/rotator_tb.vhdl
@@ -291,7 +291,6 @@ begin
 		report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
         end loop;
 
-        assert false report "end of test" severity failure;
-        wait;
+        std.env.finish;
     end process;
 end behave;
diff --git a/wishbone_bram_tb.vhdl b/wishbone_bram_tb.vhdl
index be64db6..c4ffedd 100644
--- a/wishbone_bram_tb.vhdl
+++ b/wishbone_bram_tb.vhdl
@@ -169,7 +169,6 @@ begin
         wait until rising_edge(clk);
         assert w_in.ack = '0';
 
-        assert false report "end of test" severity failure;
-        wait;
+        std.env.finish;
     end process;
 end behave;