From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 11 Nov 2019 16:51:26 +0000 (+0100)
Subject: fix fsm test with proper clock enable polarity
X-Git-Tag: working-ls180~956^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab8c521030a2c91a1e388d6f3c627a7f7dd525b2;p=yosys.git

fix fsm test with proper clock enable polarity
---

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 93a49679c..881c2e9bb 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -23,11 +23,11 @@ module  \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D),
 
 // DFFRE     D Flip-Flop with Clock Enable and Synchronous Reset
 module  \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
-module  \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule
+module  \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule
 
 // DFFNRE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
 module  \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
-module  \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule
+module  \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule
 
 // DFFS      D Flip-Flop with Synchronous Set
 module  \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
@@ -39,11 +39,11 @@ module  \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D),
 
 // DFFSE     D Flip-Flop with Clock Enable and Synchronous Set
 module  \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
-module  \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule
+module  \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule
 
 // DFFNSE    D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
 module  \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
-module  \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule
+module  \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule
 
 // DFFP      D Flip-Flop with Asynchronous Preset
 module  \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys
new file mode 100644
index 000000000..ce4504522
--- /dev/null
+++ b/tests/arch/gowin/fsm.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+#design -load postopt
+#shell