From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Apr 2019 02:42:14 +0000 (+0100)
Subject: simplify UnbufferedPipeline2
X-Git-Tag: ls180-24jan2020~1295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab910c1ad277fbbac917572927ea6ebda1c6131a;p=ieee754fpu.git

simplify UnbufferedPipeline2
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index bb1426a0..c10b34e9 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -845,8 +845,7 @@ class UnbufferedPipeline2(ControlBase):
 
         self.m.d.comb += self.n.o_valid.eq(buf_full | p_i_valid)
         self.m.d.comb += self.p._o_ready.eq(~buf_full)
-        self.m.d.sync += buf_full.eq(~self.n.i_ready_test & \
-                                        (p_i_valid | buf_full))
+        self.m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
 
         odata = Mux(buf_full, buf, self.stage.process(self.p.i_data))
         self.m.d.comb += eq(self.n.o_data, odata)