From: lkcl <lkcl@web>
Date: Sat, 8 Apr 2023 09:47:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab9375fa350d5aac16b6fed0b0da01893a8fc89a;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 25deae8bd..b467a89fb 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -106,6 +106,21 @@ for example one multiply but in-place subtracting that product from one operand
 adding it to the other.  The *in-place* aspect is strategically extremely important
 for significant reductions in Vectorised register usage, particularly for DCT.
 
+## CR Weird group
+
+Outlined in [[sv/cr_int_predication]] these instructions massively save on CR-Field
+instruction count.  Multi-bit to single-bit and vice-versa normally requiring several
+CR-ops (crand, crxor) are done in one single instruction.  The reason for their
+addition is down to SVP64 overloading CR Fields as Vector Predicate Masks.
+Reducing instruction count in hot-loops is considered high priority.
+
+An additional need is to do popcount on CR Field bit vectors but adding such instructions
+to the *Condition Register* side was deemed to be far too much. Therefore, priority
+was giiven instead to transferring several CR Field bits into GPRs, whereupon
+the full set of tandard Scalar GPR Logical Operations may be used. This strategy
+has the side-effect of keeping the CRweird group down to only five instructions.
+
+
 [[!inline pages="openpower/sv/rfc/ls012/areas.mdwn" raw=yes ]]
 
 [[!tag opf_rfc]]