From: Jacob Lifshay Date: Fri, 16 Oct 2020 22:20:40 +0000 (-0700) Subject: add cmpi X-Git-Tag: v0.2.0~7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ab9aeafa08602437538ffef322eb980faee763b1;p=power-instruction-analyzer.git add cmpi --- diff --git a/src/instr_models.rs b/src/instr_models.rs index 5eee177..ae3c23c 100644 --- a/src/instr_models.rs +++ b/src/instr_models.rs @@ -762,3 +762,25 @@ pub fn maddld(inputs: InstructionInput) -> InstructionResult { ..InstructionOutput::default() }) } + +pub fn cmpdi(inputs: InstructionInput) -> InstructionResult { + let ra = inputs.try_get_ra()? as i64; + let immediate = inputs.try_get_immediate_s16()? as i64; + let so = inputs.try_get_overflow()?.so; + let cr0 = ConditionRegister::from_ordering(ra.cmp(&immediate), so); + Ok(InstructionOutput { + cr0: Some(cr0), + ..InstructionOutput::default() + }) +} + +pub fn cmpwi(inputs: InstructionInput) -> InstructionResult { + let ra = inputs.try_get_ra()? as i32; + let immediate = inputs.try_get_immediate_s16()? as i32; + let so = inputs.try_get_overflow()?.so; + let cr0 = ConditionRegister::from_ordering(ra.cmp(&immediate), so); + Ok(InstructionOutput { + cr0: Some(cr0), + ..InstructionOutput::default() + }) +} diff --git a/src/lib.rs b/src/lib.rs index e5d26e4..0e85562 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -130,6 +130,14 @@ impl ConditionRegister { so, } } + pub fn from_ordering(ordering: Ordering, so: bool) -> Self { + Self { + lt: ordering == Ordering::Less, + gt: ordering == Ordering::Greater, + eq: ordering == Ordering::Equal, + so, + } + } } #[derive(Copy, Clone, Default, Debug, PartialEq, Serialize, Deserialize)] @@ -789,6 +797,16 @@ instructions! { fn maddld(Ra, Rb, Rc) -> (Rt) { "maddld" } + + // cmpi + #[enumerant = CmpDI] + fn cmpdi(Ra, ImmediateS16, Overflow) -> (CR0) { + "cmpdi" + } + #[enumerant = CmpWI] + fn cmpwi(Ra, ImmediateS16, Overflow) -> (CR0) { + "cmpwi" + } } // must be after instrs macro call since it uses a macro definition