From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Aug 2020 21:57:00 +0000 (+0100)
Subject: read/set pc outside of FSM so that DMI interface can get at it
X-Git-Tag: semi_working_ecp5~445
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abba163df4d0b3a5b8adf0ab23152a2993e25e9c;p=soc.git

read/set pc outside of FSM so that DMI interface can get at it
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 910598ea..3d168da6 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -114,19 +114,29 @@ class TestIssuer(Elaboratable):
         comb += self.pc_o.eq(cur_state.pc)
         ilatch = Signal(32)
 
-        # MSR (temp and latched)
+        # MSR
         msr = Signal(64, reset_less=True)
 
         # next instruction (+4 on current)
         nia = Signal(64, reset_less=True)
         comb += nia.eq(cur_state.pc + 4)
 
+        # read the PC
+        pc = Signal(64, reset_less=True)
+        with m.If(self.pc_i.ok):
+            # incoming override (start from pc_i)
+            comb += pc.eq(self.pc_i.data)
+        with m.Else():
+            # otherwise read FastRegs regfile for PC
+            comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
+            comb += pc.eq(self.fast_r_pc.data_o)
+
         # connect up debug signals
         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
         comb += core.core_stopped_i.eq(dbg.core_stop_o)
         comb += core.core_reset_i.eq(dbg.core_rst_o)
         comb += dbg.terminate_i.eq(core.core_terminate_o)
-        comb += dbg.state.pc.eq(nia)
+        comb += dbg.state.pc.eq(pc)
         comb += dbg.state.msr.eq(cur_state.msr)
 
         # temporaries
@@ -151,14 +161,6 @@ class TestIssuer(Elaboratable):
                 sync += pc_changed.eq(0)
                 with m.If(~dbg.core_stop_o):
                     # instruction allowed to go: start by reading the PC
-                    pc = Signal(64, reset_less=True)
-                    with m.If(self.pc_i.ok):
-                        # incoming override (start from pc_i)
-                        comb += pc.eq(self.pc_i.data)
-                    with m.Else():
-                        # otherwise read FastRegs regfile for PC
-                        comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
-                        comb += pc.eq(self.fast_r_pc.data_o)
                     # capture the PC and also drop it into Insn Memory
                     # we have joined a pair of combinatorial memory
                     # lookups together.  this is Generally Bad.