From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 00:17:22 +0000 (-0800)
Subject: read_aiger to also rename 0 index lut when wideports
X-Git-Tag: working-ls180~1237^2~289
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abc1c2672e2b2d2ff80b4ccf42027fd629c1ac8b;p=yosys.git

read_aiger to also rename 0 index lut when wideports
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 5c862b8f0..426e88e53 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -162,9 +162,15 @@ void AigerReader::parse_aiger()
         int width = wp.second + 1;
 
         RTLIL::Wire *wire = module->wire(name);
-        if (wire)
+        if (wire) {
+            RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
+
             module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
 
+            if (driver)
+                module->rename(driver, stringf("%slut", wire->name.c_str()));
+        }
+
         // Do not make ports with a mix of input/output into
         // wide ports
         bool port_input = false, port_output = false;
@@ -408,9 +414,15 @@ void AigerReader::parse_xaiger()
         int width = wp.second + 1;
 
         RTLIL::Wire *wire = module->wire(name);
-        if (wire)
+        if (wire) {
+            RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
+
             module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
 
+            if (driver)
+                module->rename(driver, stringf("%slut", wire->name.c_str()));
+        }
+
         // Do not make ports with a mix of input/output into
         // wide ports
         bool port_input = false, port_output = false;