From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 18:06:57 +0000 (-0700)
Subject: Use ABC to convert from AIGER to Verilog
X-Git-Tag: yosys-0.9~79^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abc40924ed5dc4aba91c7f1e83ca90f54e9eb455;p=yosys.git

Use ABC to convert from AIGER to Verilog
---

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 0a511f29c..23964a751 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -146,9 +146,10 @@ do
 		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+		elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
+			"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
 		else
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
-			frontend="verilog -noblackbox"
+			cp ../${fn} ${bn}_ref.${ext}
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then