From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Fri, 23 Aug 2019 11:19:11 +0000 (+0200)
Subject: Add constraint file for Nexys A7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abca85b03479c9d14002396a6453508710259d59;p=microwatt.git

Add constraint file for Nexys A7
---

diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc
new file mode 100644
index 0000000..b94f1bc
--- /dev/null
+++ b/fpga/nexys_a7.xdc
@@ -0,0 +1,7 @@
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
+
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports reset_n]
+
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd]
+set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]