From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 25 Jul 2017 13:13:22 +0000 (+0200)
Subject: Improve "help verific" message
X-Git-Tag: yosys-0.8~371
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abd3b4e8e78ef1b1ac71d47db9f82bc5358a4d62;p=yosys.git

Improve "help verific" message
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 883942587..dc5448f88 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1071,18 +1071,19 @@ struct VerificImporter
 
 struct VerificExtNets
 {
-	// a map from nets to the same nets one level up in the design hierarchy
-	std::map<Net*, Net*> net_level_up;
 	int portname_cnt = 0;
 	bool verbose = false;
 
+	// a map from Net to the same Net one level up in the design hierarchy
+	std::map<Net*, Net*> net_level_up;
+
 	Net *get_net_level_up(Net *net)
 	{
 		if (net_level_up.count(net) == 0)
 		{
 			Netlist *nl = net->Owner();
 
-			// Simple return if Netlist is not unique
+			// Simply return if Netlist is not unique
 			if (nl->NumOfRefs() != 1)
 				return net;
 
@@ -1172,8 +1173,7 @@ struct VerificPass : public Pass {
 		log("    verific -import [options] <top-module>..\n");
 		log("\n");
 		log("Elaborate the design for the specified top modules, import to Yosys and\n");
-		log("reset the internal state of Verific. A gate-level netlist is created\n");
-		log("when called with -gates.\n");
+		log("reset the internal state of Verific.\n");
 		log("\n");
 		log("Import options:\n");
 		log("\n");