From: Ken Raeburn <raeburn@cygnus>
Date: Fri, 27 Jan 1995 19:06:56 +0000 (+0000)
Subject: added two h8300 tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abd77746decf93cef7c77aa8be5990fbc67627d7;p=binutils-gdb.git

added two h8300 tests
---

diff --git a/gas/testsuite/gas/h8300/cmpsi2.s b/gas/testsuite/gas/h8300/cmpsi2.s
new file mode 100644
index 00000000000..ef7f03aa92b
--- /dev/null
+++ b/gas/testsuite/gas/h8300/cmpsi2.s
@@ -0,0 +1,28 @@
+# 1 "libgcc1.S"
+;; libgcc1 routines for the Hitachi h8/300 cpu.
+;; Contributed by Steve Chamberlain.
+;; sac@cygnus.com
+	.section .text
+	.align 2
+	.global ___cmpsi2
+___cmpsi2:
+	cmp.w	r2 ,r0 
+	bne	.L2
+	cmp.w	r3 ,r1 
+	bne	.L2
+	mov.w	#1,r0 
+	rts
+.L2:
+	cmp.w	r0 ,r2 
+	bgt	.L4
+	bne	.L3
+	cmp.w	r1 ,r3 
+	bls	.L3
+.L4:
+	sub.w	r0 ,r0 
+	rts
+.L3:
+	mov.w	#2,r0 
+.L5:
+	rts
+	.end
diff --git a/gas/testsuite/gas/h8300/ffxx1.d b/gas/testsuite/gas/h8300/ffxx1.d
new file mode 100644
index 00000000000..e5421525494
--- /dev/null
+++ b/gas/testsuite/gas/h8300/ffxx1.d
@@ -0,0 +1,22 @@
+#objdump: -dr
+#name: FFxx1
+
+# Test for FFxx:8 addressing.
+
+.*:     file format .*h8300.*
+
+Disassembly of section .text:
+...
+		RELOC: 0+0000 16 main
+0+0400 <main> f8 7f             mov.b	#0x7f,r0l
+0+0402 <main[+]2> 28 bb             mov.b	@0xbb:8,r0l
+0+0404 <main[+]4> 6a 88 ff b9       mov.b	r0l,@0xffb9:16
+0+0408 <main[+]8> f8 01             mov.b	#0x1,r0l
+0+040a <loop> 6a 88 ff bb       mov.b	r0l,@0xffbb:16
+0+040e <delay> 79 01 00 00       mov.w	#0x0,r1
+0+0412 <deloop> 0b 01             adds	#0x1,er1
+0+0414 <deloop[+]2> 46 00             bne	.0 \(416\)
+		RELOC: 0+0415 DISP8 deloop[+]0xffff+
+0+0416 <deloop[+]4> 12 88             rotl	r0l
+0+0418 <deloop[+]6> 40 00             bra	.0 \(41a\)
+		RELOC: 0+0419 DISP8 loop[+]0xffff+
diff --git a/gas/testsuite/gas/h8300/ffxx1.s b/gas/testsuite/gas/h8300/ffxx1.s
new file mode 100644
index 00000000000..005bd1fee03
--- /dev/null
+++ b/gas/testsuite/gas/h8300/ffxx1.s
@@ -0,0 +1,19 @@
+	.equ    p6ddr,  0xffb9          ;0x7f for output 
+	.equ    p6dr,    0xffbb
+	.equ    seed,    0x01
+	.text
+	.org    0
+reset:  .word   main            ;reset vector 
+;
+	.org    0x400
+main:   mov.b   #0x7f,r0l       ;port 6 ddr = 7F 
+	mov.b   @0xffbb:8,r0l   ;***test***
+	mov.b   r0l,@p6ddr:16
+;
+	mov.b   #seed,r0l       ;start with 0000001
+loop:   mov.b   r0l,@p6dr:16    ;output to port 6 
+delay:  mov.w   #0x0000,r1
+deloop: adds.w  #1,r1
+	bne     deloop:8        ;not = 0
+	rotl    r0l
+        bra     loop:8