From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 1 Sep 2019 10:44:24 +0000 (+0100)
Subject: add VBLOCK SVP format idea
X-Git-Tag: convert-csv-opcode-to-binary~4176
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abe14c0b36180fccb262a6d8531a912b21439925;p=libreriscv.git

add VBLOCK SVP format idea
---

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index 35d0deed1..9fe4a5722 100644
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -1,7 +1,13 @@
 # Alternative (SVPrefix) format
 
 This VBLOCK mode effectively extends [[sv_prefix_proposal]] to cover multiple
-registers.  Its advantage over the main format is that the main format requires
+registers.  The basic principle: the "prefix" specifies which of source and
+destination registers are to be considered "vectors" (or scalars), however
+where in SVPrefix that applies to only one instruction, the "vector" tag
+designations *continue to cascade* into subsequent instructions within the
+VBLOCK.
+
+Its advantage over the main format is that the main format requires
 explicit naming of the registers to be tagged (taking up 5 bits each time).
 
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