From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Aug 2020 21:05:12 +0000 (+0100)
Subject: testing 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*
X-Git-Tag: semi_working_ecp5~272^2~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abf60c9c057e7ec8005f864a16466d9b8ed56f51;p=soc.git

testing 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index e2d516bb..f8581f62 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -37,8 +37,8 @@ class LibreSoCSim(SoCSDRAM):
         platform     = Platform()
         sys_clk_freq = int(100e6)
 
-        cpu_data_width = 32
-        #cpu_data_width = 64
+        #cpu_data_width = 32
+        cpu_data_width = 64
 
         if cpu_data_width == 32:
             variant = "standard32"
@@ -53,7 +53,7 @@ class LibreSoCSim(SoCSDRAM):
             #bus_data_width           = 64,
             cpu_variant              = variant,
             csr_data_width            = 32,
-            l2_cache_size             = 0,
+            l2_size             = 0,
             uart_name                = "sim",
             with_sdram               = with_sdram,
             sdram_module          = sdram_module,
@@ -210,9 +210,9 @@ class LibreSoCSim(SoCSDRAM):
         )
 
         # limit range of pc for debug reporting
-        #self.comb += active_dbg.eq((0x5108 <= pc) & (pc <= 0x5234))
+        self.comb += active_dbg.eq((0x5108 <= pc) & (pc <= 0x5234))
         #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
-        self.comb += active_dbg.eq(1)
+        #self.comb += active_dbg.eq(1)
 
         # get the MSR
         self.sync += If(active_dbg & (uptime[0:cyclewid] == 28),
diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index f8f52d76..46d36e99 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -26,7 +26,7 @@ if __name__ == '__main__':
                          # set to 32 for instruction-memory width=32
                          imem_reg_wid=64,
                          # set to 32 to make data wishbone bus 32-bit
-                         wb_data_wid=32,
+                         #wb_data_wid=32,
                          units=units)
     dut = TestIssuer(pspec)