From: David Shah <dave@ds0.me>
Date: Tue, 21 Apr 2020 07:58:52 +0000 (+0100)
Subject: sim: Fix handling of constant-connected cell inputs at startup
X-Git-Tag: working-ls180~601^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abf81c76396d674833d1dce3f3f75a43f76e2a1f;p=yosys.git

sim: Fix handling of constant-connected cell inputs at startup

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 59bf5a712..03ca42cf3 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -128,8 +128,12 @@ struct SimInstance
 
 			for (auto &port : cell->connections()) {
 				if (cell->input(port.first))
-					for (auto bit : sigmap(port.second))
+					for (auto bit : sigmap(port.second)) {
 						upd_cells[bit].insert(cell);
+						// Make sure cell inputs connected to constants are updated in the first cycle
+						if (bit.wire == nullptr)
+							dirty_bits.insert(bit);
+					}
 			}
 
 			if (cell->type.in(ID($dff))) {
diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys
new file mode 100644
index 000000000..d778b92cd
--- /dev/null
+++ b/tests/various/sim_const.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+
+module top(input clk, output reg [1:0] q);
+	wire [1:0] x = 2'b10;
+	always @(posedge clk)
+		q <= x & 2'b11;
+endmodule
+EOT
+
+proc
+sim -clock clk -n 1 -w top
+select -assert-count 1 a:init=2'b10 top/q %i
+