From: lkcl <lkcl@web>
Date: Wed, 24 May 2023 11:45:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=abfd0986a883582e5c607885bad4e17e4ff425cb;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 0080ee163..e8bcc4449 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -166,7 +166,8 @@ loop:
 ### Loop using Rc=1
 
 In this example, the `setvl.` instruction enabled Rc=1, which
-sets CR0.eq when VL becomes zero.
+sets CR0.eq when VL becomes zero. Testing of `r4` (cmpi) is thus redundant
+saving one instruction.
 
 ```
     my_fn:
@@ -188,7 +189,7 @@ Up to 64 FPRs will be loaded, here.  `r3` is set one per bit for each
 FP register required to be loaded.  The block of memory from which the
 registers are loaded is contiguous (no gaps): any FP register which has
 a corresponding zero bit in `r3` is *unaltered*.  In essence this is a
-selective LD-multi with "Scatter" capability.
+selective LD-multi with "Scatter" (`VCOMPRESS`) capability.
 
 ```
     setvli r0, MVL=64, VL=64