From: Dave Brolley Date: Wed, 15 Jun 2005 16:23:54 +0000 (+0000) Subject: 2005-06-15 Dave Brolley X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac18822241cf8b9a448e3f4d92b3769a7162626a;p=binutils-gdb.git 2005-06-15 Dave Brolley Contribute Morpho ms1 on behalf of Red Hat * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h: New files, Morpho ms1 target. 2004-05-14 Stan Cox * disassemble.c (ARCH_ms1): Define. (disassembler): Handle bfd_arch_ms1 2004-05-13 Michael Snyder * Makefile.am, Makefile.in: Add ms1 target. * configure.in: Ditto. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 94452d8d275..0d6209a9d4c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,19 @@ +2005-06-15 Dave Brolley + + Contribute Morpho ms1 on behalf of Red Hat + * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c, + ms1-opc.h: New files, Morpho ms1 target. + + 2004-05-14 Stan Cox + + * disassemble.c (ARCH_ms1): Define. + (disassembler): Handle bfd_arch_ms1 + + 2004-05-13 Michael Snyder + + * Makefile.am, Makefile.in: Add ms1 target. + * configure.in: Ditto. + 2005-06-08 Zack Weinberg * arm-opc.h: Delete; fold contents into ... diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 51f8df76dad..5218420cd46 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -34,6 +34,7 @@ HFILES = \ iq2000-desc.h iq2000-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ + ms1-desc.h ms1-opc.h \ openrisc-desc.h openrisc-opc.h \ sh-opc.h \ sh64-opc.h \ @@ -127,6 +128,11 @@ CFILES = \ m10300-opc.c \ mmix-dis.c \ mmix-opc.c \ + ms1-asm.c \ + ms1-desc.c \ + ms1-dis.c \ + ms1-ibld.c \ + ms1-opc.c \ ns32k-dis.c \ openrisc-asm.c \ openrisc-desc.c \ @@ -241,6 +247,11 @@ ALL_MACHINES = \ mips16-opc.lo \ mmix-dis.lo \ mmix-opc.lo \ + ms1-asm.lo \ + ms1-desc.lo \ + ms1-dis.lo \ + ms1-ibld.lo \ + ms1-opc.lo \ msp430-dis.lo \ ns32k-dis.lo \ openrisc-asm.lo \ @@ -351,7 +362,7 @@ uninstall_libopcodes: CLEANFILES = \ stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-iq2000 stamp-xstormy16 \ + stamp-iq2000 stamp-ms1 stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -367,13 +378,14 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16 +CGEN_CPUS = fr30 frv ip2k m32r ms1 openrisc xstormy16 if CGEN_MAINT IP2K_DEPS = stamp-ip2k M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 FRV_DEPS = stamp-frv +MS1_DEPS = stamp-ms1 OPENRISC_DEPS = stamp-openrisc IQ2000_DEPS = stamp-iq2000 XSTORMY16_DEPS = stamp-xstormy16 @@ -382,6 +394,7 @@ IP2K_DEPS = M32R_DEPS = FR30_DEPS = FRV_DEPS = +MS1_DEPS = OPENRISC_DEPS = IQ2000_DEPS = XSTORMY16_DEPS = @@ -423,12 +436,16 @@ stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) @true -# .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so -# copy those file to the regular place. stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc $(MAKE) run-cgen arch=frv prefix=frv options= \ archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= +$(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MS1_DEPS) + @true +stamp-ms1: $(CGENDEPS) $(CPUDIR)/ms1.cpu $(CPUDIR)/ms1.opc + $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \ + archfile=$(CPUDIR)/ms1.cpu opcfile=$(CPUDIR)/ms1.opc extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -746,6 +763,25 @@ mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ opintl.h mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h +ms1-asm.lo: ms1-asm.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ms1-desc.lo: ms1-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h +ms1-dis.lo: ms1-dis.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/libiberty.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h opintl.h +ms1-ibld.lo: ms1-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +ms1-opc.lo: ms1-opc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \ $(INCDIR)/opcode/ns32k.h opintl.h diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index c32eca31f72..02159ae19e5 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -255,6 +255,7 @@ HFILES = \ iq2000-desc.h iq2000-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ + ms1-desc.h ms1-opc.h \ openrisc-desc.h openrisc-opc.h \ sh-opc.h \ sh64-opc.h \ @@ -349,6 +350,11 @@ CFILES = \ m10300-opc.c \ mmix-dis.c \ mmix-opc.c \ + ms1-asm.c \ + ms1-desc.c \ + ms1-dis.c \ + ms1-ibld.c \ + ms1-opc.c \ ns32k-dis.c \ openrisc-asm.c \ openrisc-desc.c \ @@ -463,6 +469,11 @@ ALL_MACHINES = \ mips16-opc.lo \ mmix-dis.lo \ mmix-opc.lo \ + ms1-asm.lo \ + ms1-desc.lo \ + ms1-dis.lo \ + ms1-ibld.lo \ + ms1-opc.lo \ msp430-dis.lo \ ns32k-dis.lo \ openrisc-asm.lo \ @@ -527,7 +538,7 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-iq2000 stamp-xstormy16 \ + stamp-iq2000 stamp-ms1 stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 CGENDIR = @cgendir@ @@ -541,7 +552,7 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16 +CGEN_CPUS = fr30 frv ip2k m32r ms1 openrisc xstormy16 @CGEN_MAINT_FALSE@IP2K_DEPS = @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k @CGEN_MAINT_FALSE@M32R_DEPS = @@ -550,6 +561,8 @@ CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16 @CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30 @CGEN_MAINT_FALSE@FRV_DEPS = @CGEN_MAINT_TRUE@FRV_DEPS = stamp-frv +@CGEN_MAINT_FALSE@MS1_DEPS = +@CGEN_MAINT_TRUE@MS1_DEPS = stamp-ms1 @CGEN_MAINT_FALSE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@OPENRISC_DEPS = stamp-openrisc @CGEN_MAINT_FALSE@IQ2000_DEPS = @@ -953,12 +966,16 @@ stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) @true -# .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so -# copy those file to the regular place. stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc $(MAKE) run-cgen arch=frv prefix=frv options= \ archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= +$(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MS1_DEPS) + @true +stamp-ms1: $(CGENDEPS) $(srcdir)/../cpu/ms1.cpu $(srcdir)/../cpu/ms1.opc + $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \ + archfile=$(srcdir)/../cpu/ms1.cpu opcfile=$(srcdir)/../cpu/ms1.opc extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -1276,6 +1293,25 @@ mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ opintl.h mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h +ms1-asm.lo: ms1-asm.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ms1-desc.lo: ms1-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h +ms1-dis.lo: ms1-dis.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/libiberty.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h opintl.h +ms1-ibld.lo: ms1-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +ms1-opc.lo: ms1-opc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \ $(INCDIR)/opcode/ns32k.h opintl.h diff --git a/opcodes/configure b/opcodes/configure index 7ec35920418..161ea780bf2 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -8727,6 +8727,7 @@ if test x${all_targets} = xfalse ; then bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_ms1_arch) ta="$ta ms1-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;; bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index aff4f347b63..f437558675b 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -187,6 +187,7 @@ if test x${all_targets} = xfalse ; then bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_ms1_arch) ta="$ta ms1-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;; bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 20e5424053f..0d210e1921d 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -51,6 +51,7 @@ #define ARCH_mmix #define ARCH_mn10200 #define ARCH_mn10300 +#define ARCH_ms1 #define ARCH_msp430 #define ARCH_ns32k #define ARCH_openrisc @@ -233,6 +234,11 @@ disassembler (abfd) disassemble = print_insn_maxq_little; break; #endif +#ifdef ARCH_ms1 + case bfd_arch_ms1: + disassemble = print_insn_ms1; + break; +#endif #ifdef ARCH_msp430 case bfd_arch_msp430: disassemble = print_insn_msp430; diff --git a/opcodes/ms1-asm.c b/opcodes/ms1-asm.c new file mode 100644 index 00000000000..0b65226f19b --- /dev/null +++ b/opcodes/ms1-asm.c @@ -0,0 +1,978 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ms1-desc.h" +#include "ms1-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static int signed_out_of_bounds (long); +static const char * parse_imm16 (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_dup (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_ball (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_xmode (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_rc (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_cbrb (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_rbbc (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_type (CGEN_CPU_DESC, const char **, int, long *); + +/* Range checking for signed numbers. Returns 0 if acceptable + and 1 if the value is out of bounds for a signed quantity. */ + +static int +signed_out_of_bounds (long val) +{ + if ((val < -32768) || (val > 32767)) + return 1; + return 0; +} + +static const char * +parse_imm16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + /* Is it a control transfer instructions? */ + if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16O) + { + code = BFD_RELOC_16_PCREL; + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + if (signed_out_of_bounds (value)) + errmsg = _("Operand out of range. Must be between -32768 and 32767."); + } + *valuep = value; + return errmsg; + } + + /* If it's not a control transfer instruction, then + we have to check for %OP relocating operators. */ + if (strncmp (*strp, "%hi16", 5) == 0) + { + *strp += 5; + code = BFD_RELOC_HI16; + } + else if (strncmp (*strp, "%lo16", 5) == 0) + { + *strp += 5; + code = BFD_RELOC_LO16; + } + + /* If we found a %OP relocating operator, then parse it as an address. + If not, we need to parse it as an integer, either signed or unsigned + depending on which operand type we have. */ + if (code != BFD_RELOC_NONE) + { + /* %OP relocating operator found. */ + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + switch (result_type) + { + case (CGEN_PARSE_OPERAND_RESULT_NUMBER): + if (code == BFD_RELOC_HI16) + value = (value >> 16) & 0xFFFF; + else if (code == BFD_RELOC_LO16) + value = value & 0xFFFF; + else + errmsg = _("Biiiig Trouble in parse_imm16!"); + break; + + case (CGEN_PARSE_OPERAND_RESULT_QUEUED): + /* No special processing for this case. */ + break; + + default: + errmsg = _("%operator operand is not a symbol"); + break; + } + } + *valuep = value; + } + else + { + /* Parse hex values like 0xffff as unsigned, and sign extend + them manually. */ + int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16); + + if ((*strp)[0] == '0' + && ((*strp)[1] == 'x' || (*strp)[1] == 'X')) + parse_signed = 0; + + /* No relocating operator. Parse as an number. */ + if (parse_signed) + { + /* Parse as as signed integer. */ + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); + + if (errmsg == NULL) + { +#if 0 + /* Manual range checking is needed for the signed case. */ + if (*valuep & 0x8000) + value = 0xffff0000 | *valuep; + else + value = *valuep; + + if (signed_out_of_bounds (value)) + errmsg = _("Operand out of range. Must be between -32768 and 32767."); + /* Truncate to 16 bits. This is necessary + because cgen will have sign extended *valuep. */ + *valuep &= 0xFFFF; +#endif + } + } + else + { + /* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */ + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + if (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16 + && *valuep >= 0x8000 + && *valuep <= 0xffff) + *valuep -= 0x10000; + } + } + + return errmsg; +} + + +static const char * +parse_dup (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "dup", 3) == 0 || strncmp (*strp, "DUP", 3) == 0) + { + *strp += 3; + *valuep = 1; + } + else if (strncmp (*strp, "xx", 2) == 0 || strncmp (*strp, "XX", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + + +static const char * +parse_ball (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "all", 3) == 0 || strncmp (*strp, "ALL", 3) == 0) + { + *strp += 3; + *valuep = 1; + } + else if (strncmp (*strp, "one", 3) == 0 || strncmp (*strp, "ONE", 3) == 0) + { + *strp += 3; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_xmode (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "pm", 2) == 0 || strncmp (*strp, "PM", 2) == 0) + { + *strp += 2; + *valuep = 1; + } + else if (strncmp (*strp, "xm", 2) == 0 || strncmp (*strp, "XM", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_rc (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "r", 1) == 0 || strncmp (*strp, "R", 1) == 0) + { + *strp += 1; + *valuep = 1; + } + else if (strncmp (*strp, "c", 1) == 0 || strncmp (*strp, "C", 1) == 0) + { + *strp += 1; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_cbrb (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "rb", 2) == 0 || strncmp (*strp, "RB", 2) == 0) + { + *strp += 2; + *valuep = 1; + } + else if (strncmp (*strp, "cb", 2) == 0 || strncmp (*strp, "CB", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_rbbc (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "rt", 2) == 0 || strncmp (*strp, "RT", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else if (strncmp (*strp, "br1", 3) == 0 || strncmp (*strp, "BR1", 3) == 0) + { + *strp += 3; + *valuep = 1; + } + else if (strncmp (*strp, "br2", 3) == 0 || strncmp (*strp, "BR2", 3) == 0) + { + *strp += 3; + *valuep = 2; + } + else if (strncmp (*strp, "cs", 2) == 0 || strncmp (*strp, "CS", 2) == 0) + { + *strp += 2; + *valuep = 3; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_type (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "odd", 3) == 0 || strncmp (*strp, "ODD", 3) == 0) + { + *strp += 3; + *valuep = 0; + } + else if (strncmp (*strp, "even", 4) == 0 || strncmp (*strp, "EVEN", 4) == 0) + { + *strp += 4; + *valuep = 1; + } + else if (strncmp (*strp, "oe", 2) == 0 || strncmp (*strp, "OE", 2) == 0) + { + *strp += 2; + *valuep = 2; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + if ((errmsg == NULL) && (*valuep == 3)) + errmsg = _("invalid operand. type may have values 0,1,2 only."); + + return errmsg; +} + +/* -- dis.c */ + +const char * ms1_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +ms1_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case MS1_OPERAND_A23 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_A23, (unsigned long *) (& fields->f_a23)); + break; + case MS1_OPERAND_BALL : + errmsg = parse_ball (cd, strp, MS1_OPERAND_BALL, (unsigned long *) (& fields->f_ball)); + break; + case MS1_OPERAND_BALL2 : + errmsg = parse_ball (cd, strp, MS1_OPERAND_BALL2, (unsigned long *) (& fields->f_ball2)); + break; + case MS1_OPERAND_BANKADDR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BANKADDR, (unsigned long *) (& fields->f_bankaddr)); + break; + case MS1_OPERAND_BRC : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC, (unsigned long *) (& fields->f_brc)); + break; + case MS1_OPERAND_BRC2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2)); + break; + case MS1_OPERAND_CBRB : + errmsg = parse_cbrb (cd, strp, MS1_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb)); + break; + case MS1_OPERAND_CBS : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CBS, (unsigned long *) (& fields->f_cbs)); + break; + case MS1_OPERAND_CBX : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CBX, (unsigned long *) (& fields->f_cbx)); + break; + case MS1_OPERAND_CCB : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CCB, (unsigned long *) (& fields->f_ccb)); + break; + case MS1_OPERAND_CDB : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CDB, (unsigned long *) (& fields->f_cdb)); + break; + case MS1_OPERAND_CELL : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CELL, (unsigned long *) (& fields->f_cell)); + break; + case MS1_OPERAND_COLNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_COLNUM, (unsigned long *) (& fields->f_colnum)); + break; + case MS1_OPERAND_CONTNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CONTNUM, (unsigned long *) (& fields->f_contnum)); + break; + case MS1_OPERAND_CR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CR, (unsigned long *) (& fields->f_cr)); + break; + case MS1_OPERAND_CTXDISP : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CTXDISP, (unsigned long *) (& fields->f_ctxdisp)); + break; + case MS1_OPERAND_DUP : + errmsg = parse_dup (cd, strp, MS1_OPERAND_DUP, (unsigned long *) (& fields->f_dup)); + break; + case MS1_OPERAND_FBDISP : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_FBDISP, (unsigned long *) (& fields->f_fbdisp)); + break; + case MS1_OPERAND_FBINCR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_FBINCR, (unsigned long *) (& fields->f_fbincr)); + break; + case MS1_OPERAND_FRDR : + errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_dr); + break; + case MS1_OPERAND_FRDRRR : + errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_drrr); + break; + case MS1_OPERAND_FRSR1 : + errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_sr1); + break; + case MS1_OPERAND_FRSR2 : + errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_sr2); + break; + case MS1_OPERAND_ID : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ID, (unsigned long *) (& fields->f_id)); + break; + case MS1_OPERAND_IMM16 : + errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16, (long *) (& fields->f_imm16s)); + break; + case MS1_OPERAND_IMM16O : + errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s)); + break; + case MS1_OPERAND_IMM16Z : + errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16Z, (unsigned long *) (& fields->f_imm16u)); + break; + case MS1_OPERAND_INCAMT : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_INCAMT, (unsigned long *) (& fields->f_incamt)); + break; + case MS1_OPERAND_INCR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_INCR, (unsigned long *) (& fields->f_incr)); + break; + case MS1_OPERAND_LENGTH : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_LENGTH, (unsigned long *) (& fields->f_length)); + break; + case MS1_OPERAND_MASK : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK, (unsigned long *) (& fields->f_mask)); + break; + case MS1_OPERAND_MASK1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK1, (unsigned long *) (& fields->f_mask1)); + break; + case MS1_OPERAND_MODE : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MODE, (unsigned long *) (& fields->f_mode)); + break; + case MS1_OPERAND_PERM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_PERM, (unsigned long *) (& fields->f_perm)); + break; + case MS1_OPERAND_RBBC : + errmsg = parse_rbbc (cd, strp, MS1_OPERAND_RBBC, (unsigned long *) (& fields->f_rbbc)); + break; + case MS1_OPERAND_RC : + errmsg = parse_rc (cd, strp, MS1_OPERAND_RC, (unsigned long *) (& fields->f_rc)); + break; + case MS1_OPERAND_RC1 : + errmsg = parse_rc (cd, strp, MS1_OPERAND_RC1, (unsigned long *) (& fields->f_rc1)); + break; + case MS1_OPERAND_RC2 : + errmsg = parse_rc (cd, strp, MS1_OPERAND_RC2, (unsigned long *) (& fields->f_rc2)); + break; + case MS1_OPERAND_RCNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum)); + break; + case MS1_OPERAND_RDA : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RDA, (unsigned long *) (& fields->f_rda)); + break; + case MS1_OPERAND_ROWNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM, (unsigned long *) (& fields->f_rownum)); + break; + case MS1_OPERAND_ROWNUM1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM1, (unsigned long *) (& fields->f_rownum1)); + break; + case MS1_OPERAND_ROWNUM2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM2, (unsigned long *) (& fields->f_rownum2)); + break; + case MS1_OPERAND_SIZE : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_SIZE, (unsigned long *) (& fields->f_size)); + break; + case MS1_OPERAND_TYPE : + errmsg = parse_type (cd, strp, MS1_OPERAND_TYPE, (unsigned long *) (& fields->f_type)); + break; + case MS1_OPERAND_WR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_WR, (unsigned long *) (& fields->f_wr)); + break; + case MS1_OPERAND_XMODE : + errmsg = parse_xmode (cd, strp, MS1_OPERAND_XMODE, (unsigned long *) (& fields->f_xmode)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const ms1_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +ms1_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + ms1_cgen_init_opcode_table (cd); + ms1_cgen_init_ibld_table (cd); + cd->parse_handlers = & ms1_cgen_parse_handlers[0]; + cd->parse_operand = ms1_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by ms1_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +ms1_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +ms1_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! ms1_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +ms1_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! ms1_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/ms1-desc.c b/opcodes/ms1-desc.c new file mode 100644 index 00000000000..2108fd421b1 --- /dev/null +++ b/opcodes/ms1-desc.c @@ -0,0 +1,1284 @@ +/* CPU data for ms1. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ms1-desc.h" +#include "ms1-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "ms1", MACH_MS1 }, + { "ms1_003", MACH_MS1_003 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "ms1", ISA_MS1 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, + { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] }, + { "AL-INSN", &bool_attr[0], &bool_attr[0] }, + { "IO-INSN", &bool_attr[0], &bool_attr[0] }, + { "BR-INSN", &bool_attr[0], &bool_attr[0] }, + { "USES-FRDR", &bool_attr[0], &bool_attr[0] }, + { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] }, + { "USES-FRSR1", &bool_attr[0], &bool_attr[0] }, + { "USES-FRSR2", &bool_attr[0], &bool_attr[0] }, + { "SKIPA", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA ms1_cgen_isa_table[] = { + { "ms1", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH ms1_cgen_mach_table[] = { + { "ms1", "ms1", MACH_MS1, 0 }, + { "ms1-003", "ms1-003", MACH_MS1_003, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY ms1_cgen_opval_msys_syms_entries[] = +{ + { "DUP", 1, {0, {0}}, 0, 0 }, + { "XX", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD ms1_cgen_opval_msys_syms = +{ + & ms1_cgen_opval_msys_syms_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY ms1_cgen_opval_h_spr_entries[] = +{ + { "R0", 0, {0, {0}}, 0, 0 }, + { "R1", 1, {0, {0}}, 0, 0 }, + { "R2", 2, {0, {0}}, 0, 0 }, + { "R3", 3, {0, {0}}, 0, 0 }, + { "R4", 4, {0, {0}}, 0, 0 }, + { "R5", 5, {0, {0}}, 0, 0 }, + { "R6", 6, {0, {0}}, 0, 0 }, + { "R7", 7, {0, {0}}, 0, 0 }, + { "R8", 8, {0, {0}}, 0, 0 }, + { "R9", 9, {0, {0}}, 0, 0 }, + { "R10", 10, {0, {0}}, 0, 0 }, + { "R11", 11, {0, {0}}, 0, 0 }, + { "R12", 12, {0, {0}}, 0, 0 }, + { "fp", 12, {0, {0}}, 0, 0 }, + { "R13", 13, {0, {0}}, 0, 0 }, + { "sp", 13, {0, {0}}, 0, 0 }, + { "R14", 14, {0, {0}}, 0, 0 }, + { "ra", 14, {0, {0}}, 0, 0 }, + { "R15", 15, {0, {0}}, 0, 0 }, + { "ira", 15, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD ms1_cgen_opval_h_spr = +{ + & ms1_cgen_opval_h_spr_entries[0], + 20, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY ms1_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & ms1_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & ms1_cgen_ifld_table[0]; +} + +/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & ms1_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of ms1_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & ms1_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of ms1_cgen_cpu_open to rebuild the tables. */ + +static void +ms1_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & ms1_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & ms1_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "ms1_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (ms1_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "ms1_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "ms1_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = ms1_cgen_rebuild_tables; + ms1_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to ms1_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +ms1_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return ms1_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +ms1_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/ms1-desc.h b/opcodes/ms1-desc.h new file mode 100644 index 00000000000..9dfd4da44d2 --- /dev/null +++ b/opcodes/ms1-desc.h @@ -0,0 +1,246 @@ +/* CPU data header for ms1. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MS1_CPU_H +#define MS1_CPU_H + +#define CGEN_ARCH ms1 + +/* Given symbol S, return ms1_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) ms1##_cgen_##s +#else +#define CGEN_SYM(s) ms1/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_MS1BF +#define HAVE_CPU_MS1_003BF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 40 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 14 + +/* Enums. */ + +/* Enum declaration for msys enums. */ +typedef enum insn_msys { + MSYS_NO, MSYS_YES +} INSN_MSYS; + +/* Enum declaration for opc enums. */ +typedef enum insn_opc { + OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3 + , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10 + , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14 + , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24 + , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28 + , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LDW = 32, OPC_STW = 33 + , OPC_EI = 48, OPC_DI = 49, OPC_SI = 50, OPC_RETI = 51 + , OPC_BREAK = 52, OPC_IFLUSH = 53 +} INSN_OPC; + +/* Enum declaration for msopc enums. */ +typedef enum insn_msopc { + MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB + , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI + , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI + , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB + , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB + , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR + , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR + , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS +} INSN_MSOPC; + +/* Enum declaration for imm enums. */ +typedef enum insn_imm { + IMM_NO, IMM_YES +} INSN_IMM; + +/* Enum declaration for . */ +typedef enum msys_syms { + H_NIL_DUP = 1, H_NIL_XX = 0 +} MSYS_SYMS; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_MS1, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for ms1 ifield types. */ +typedef enum ifield_type { + MS1_F_NIL, MS1_F_ANYOF, MS1_F_MSYS, MS1_F_OPC + , MS1_F_IMM, MS1_F_UU24, MS1_F_SR1, MS1_F_SR2 + , MS1_F_DR, MS1_F_DRRR, MS1_F_IMM16U, MS1_F_IMM16S + , MS1_F_IMM16A, MS1_F_UU4A, MS1_F_UU4B, MS1_F_UU12 + , MS1_F_UU16, MS1_F_MSOPC, MS1_F_UU_26_25, MS1_F_MASK + , MS1_F_BANKADDR, MS1_F_RDA, MS1_F_UU_2_25, MS1_F_RBBC + , MS1_F_PERM, MS1_F_MODE, MS1_F_UU_1_24, MS1_F_WR + , MS1_F_FBINCR, MS1_F_UU_2_23, MS1_F_XMODE, MS1_F_A23 + , MS1_F_MASK1, MS1_F_CR, MS1_F_TYPE, MS1_F_INCAMT + , MS1_F_CBS, MS1_F_UU_1_19, MS1_F_BALL, MS1_F_COLNUM + , MS1_F_BRC, MS1_F_INCR, MS1_F_FBDISP, MS1_F_UU_4_15 + , MS1_F_LENGTH, MS1_F_UU_1_15, MS1_F_RC, MS1_F_RCNUM + , MS1_F_ROWNUM, MS1_F_CBX, MS1_F_ID, MS1_F_SIZE + , MS1_F_ROWNUM1, MS1_F_UU_3_11, MS1_F_RC1, MS1_F_CCB + , MS1_F_CBRB, MS1_F_CDB, MS1_F_ROWNUM2, MS1_F_CELL + , MS1_F_UU_3_9, MS1_F_CONTNUM, MS1_F_UU_1_6, MS1_F_DUP + , MS1_F_RC2, MS1_F_CTXDISP, MS1_F_MSYSFRSR2, MS1_F_BRC2 + , MS1_F_BALL2, MS1_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) MS1_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for ms1 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for ms1 operand types. */ +typedef enum cgen_operand_type { + MS1_OPERAND_PC, MS1_OPERAND_FRSR1, MS1_OPERAND_FRSR2, MS1_OPERAND_FRDR + , MS1_OPERAND_FRDRRR, MS1_OPERAND_IMM16, MS1_OPERAND_IMM16Z, MS1_OPERAND_IMM16O + , MS1_OPERAND_RC, MS1_OPERAND_RCNUM, MS1_OPERAND_CONTNUM, MS1_OPERAND_RBBC + , MS1_OPERAND_COLNUM, MS1_OPERAND_ROWNUM, MS1_OPERAND_ROWNUM1, MS1_OPERAND_ROWNUM2 + , MS1_OPERAND_RC1, MS1_OPERAND_RC2, MS1_OPERAND_CBRB, MS1_OPERAND_CELL + , MS1_OPERAND_DUP, MS1_OPERAND_CTXDISP, MS1_OPERAND_FBDISP, MS1_OPERAND_TYPE + , MS1_OPERAND_MASK, MS1_OPERAND_BANKADDR, MS1_OPERAND_INCAMT, MS1_OPERAND_XMODE + , MS1_OPERAND_MASK1, MS1_OPERAND_BALL, MS1_OPERAND_BRC, MS1_OPERAND_RDA + , MS1_OPERAND_WR, MS1_OPERAND_BALL2, MS1_OPERAND_BRC2, MS1_OPERAND_PERM + , MS1_OPERAND_A23, MS1_OPERAND_CR, MS1_OPERAND_CBS, MS1_OPERAND_INCR + , MS1_OPERAND_LENGTH, MS1_OPERAND_CBX, MS1_OPERAND_CCB, MS1_OPERAND_CDB + , MS1_OPERAND_MODE, MS1_OPERAND_ID, MS1_OPERAND_SIZE, MS1_OPERAND_FBINCR + , MS1_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 48 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS + , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_USES_FRDR + , CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA + , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld ms1_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD ms1_cgen_opval_h_spr; + +extern const CGEN_HW_ENTRY ms1_cgen_hw_table[]; + + + +#endif /* MS1_CPU_H */ diff --git a/opcodes/ms1-dis.c b/opcodes/ms1-dis.c new file mode 100644 index 00000000000..0dd51012b99 --- /dev/null +++ b/opcodes/ms1-dis.c @@ -0,0 +1,678 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 +Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "ms1-desc.h" +#include "ms1-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here */ + +/* -- dis.c */ +static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); + +static void +print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "$%x", value); + + if (0) + print_normal (cd, dis_info, value, attrs, pc, length); +} + + +/* -- */ + +void ms1_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +ms1_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case MS1_OPERAND_A23 : + print_dollarhex (cd, info, fields->f_a23, 0, pc, length); + break; + case MS1_OPERAND_BALL : + print_dollarhex (cd, info, fields->f_ball, 0, pc, length); + break; + case MS1_OPERAND_BALL2 : + print_dollarhex (cd, info, fields->f_ball2, 0, pc, length); + break; + case MS1_OPERAND_BANKADDR : + print_dollarhex (cd, info, fields->f_bankaddr, 0, pc, length); + break; + case MS1_OPERAND_BRC : + print_dollarhex (cd, info, fields->f_brc, 0, pc, length); + break; + case MS1_OPERAND_BRC2 : + print_dollarhex (cd, info, fields->f_brc2, 0, pc, length); + break; + case MS1_OPERAND_CBRB : + print_dollarhex (cd, info, fields->f_cbrb, 0, pc, length); + break; + case MS1_OPERAND_CBS : + print_dollarhex (cd, info, fields->f_cbs, 0, pc, length); + break; + case MS1_OPERAND_CBX : + print_dollarhex (cd, info, fields->f_cbx, 0, pc, length); + break; + case MS1_OPERAND_CCB : + print_dollarhex (cd, info, fields->f_ccb, 0, pc, length); + break; + case MS1_OPERAND_CDB : + print_dollarhex (cd, info, fields->f_cdb, 0, pc, length); + break; + case MS1_OPERAND_CELL : + print_dollarhex (cd, info, fields->f_cell, 0, pc, length); + break; + case MS1_OPERAND_COLNUM : + print_dollarhex (cd, info, fields->f_colnum, 0, pc, length); + break; + case MS1_OPERAND_CONTNUM : + print_dollarhex (cd, info, fields->f_contnum, 0, pc, length); + break; + case MS1_OPERAND_CR : + print_dollarhex (cd, info, fields->f_cr, 0, pc, length); + break; + case MS1_OPERAND_CTXDISP : + print_dollarhex (cd, info, fields->f_ctxdisp, 0, pc, length); + break; + case MS1_OPERAND_DUP : + print_dollarhex (cd, info, fields->f_dup, 0, pc, length); + break; + case MS1_OPERAND_FBDISP : + print_dollarhex (cd, info, fields->f_fbdisp, 0, pc, length); + break; + case MS1_OPERAND_FBINCR : + print_dollarhex (cd, info, fields->f_fbincr, 0, pc, length); + break; + case MS1_OPERAND_FRDR : + print_keyword (cd, info, & ms1_cgen_opval_h_spr, fields->f_dr, 0|(1<f_drrr, 0|(1<f_sr1, 0|(1<f_sr2, 0|(1<f_id, 0, pc, length); + break; + case MS1_OPERAND_IMM16 : + print_dollarhex (cd, info, fields->f_imm16s, 0|(1<f_imm16s, 0, pc, length); + break; + case MS1_OPERAND_IMM16Z : + print_dollarhex (cd, info, fields->f_imm16u, 0, pc, length); + break; + case MS1_OPERAND_INCAMT : + print_dollarhex (cd, info, fields->f_incamt, 0, pc, length); + break; + case MS1_OPERAND_INCR : + print_dollarhex (cd, info, fields->f_incr, 0, pc, length); + break; + case MS1_OPERAND_LENGTH : + print_dollarhex (cd, info, fields->f_length, 0, pc, length); + break; + case MS1_OPERAND_MASK : + print_dollarhex (cd, info, fields->f_mask, 0, pc, length); + break; + case MS1_OPERAND_MASK1 : + print_dollarhex (cd, info, fields->f_mask1, 0, pc, length); + break; + case MS1_OPERAND_MODE : + print_dollarhex (cd, info, fields->f_mode, 0, pc, length); + break; + case MS1_OPERAND_PERM : + print_dollarhex (cd, info, fields->f_perm, 0, pc, length); + break; + case MS1_OPERAND_RBBC : + print_dollarhex (cd, info, fields->f_rbbc, 0, pc, length); + break; + case MS1_OPERAND_RC : + print_dollarhex (cd, info, fields->f_rc, 0, pc, length); + break; + case MS1_OPERAND_RC1 : + print_dollarhex (cd, info, fields->f_rc1, 0, pc, length); + break; + case MS1_OPERAND_RC2 : + print_dollarhex (cd, info, fields->f_rc2, 0, pc, length); + break; + case MS1_OPERAND_RCNUM : + print_dollarhex (cd, info, fields->f_rcnum, 0, pc, length); + break; + case MS1_OPERAND_RDA : + print_dollarhex (cd, info, fields->f_rda, 0, pc, length); + break; + case MS1_OPERAND_ROWNUM : + print_dollarhex (cd, info, fields->f_rownum, 0, pc, length); + break; + case MS1_OPERAND_ROWNUM1 : + print_dollarhex (cd, info, fields->f_rownum1, 0, pc, length); + break; + case MS1_OPERAND_ROWNUM2 : + print_dollarhex (cd, info, fields->f_rownum2, 0, pc, length); + break; + case MS1_OPERAND_SIZE : + print_dollarhex (cd, info, fields->f_size, 0, pc, length); + break; + case MS1_OPERAND_TYPE : + print_dollarhex (cd, info, fields->f_type, 0, pc, length); + break; + case MS1_OPERAND_WR : + print_dollarhex (cd, info, fields->f_wr, 0, pc, length); + break; + case MS1_OPERAND_XMODE : + print_dollarhex (cd, info, fields->f_xmode, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const ms1_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +ms1_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + ms1_cgen_init_opcode_table (cd); + ms1_cgen_init_ibld_table (cd); + cd->print_handlers = & ms1_cgen_print_handlers[0]; + cd->print_operand = ms1_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + ms1_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! ms1_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_ms1 (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_ms1 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = ms1_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + ms1_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/ms1-ibld.c b/opcodes/ms1-ibld.c new file mode 100644 index 00000000000..fc848605f96 --- /dev/null +++ b/opcodes/ms1-ibld.c @@ -0,0 +1,1618 @@ +/* Instruction building/extraction support for ms1. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "ms1-desc.h" +#include "ms1-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * ms1_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +ms1_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MS1_OPERAND_A23 : + errmsg = insert_normal (cd, fields->f_a23, 0, 0, 23, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_BALL : + errmsg = insert_normal (cd, fields->f_ball, 0, 0, 19, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_BALL2 : + errmsg = insert_normal (cd, fields->f_ball2, 0, 0, 15, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_BANKADDR : + errmsg = insert_normal (cd, fields->f_bankaddr, 0, 0, 25, 13, 32, total_length, buffer); + break; + case MS1_OPERAND_BRC : + errmsg = insert_normal (cd, fields->f_brc, 0, 0, 18, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_BRC2 : + errmsg = insert_normal (cd, fields->f_brc2, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_CBRB : + errmsg = insert_normal (cd, fields->f_cbrb, 0, 0, 10, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_CBS : + errmsg = insert_normal (cd, fields->f_cbs, 0, 0, 19, 2, 32, total_length, buffer); + break; + case MS1_OPERAND_CBX : + errmsg = insert_normal (cd, fields->f_cbx, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_CCB : + errmsg = insert_normal (cd, fields->f_ccb, 0, 0, 11, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_CDB : + errmsg = insert_normal (cd, fields->f_cdb, 0, 0, 10, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_CELL : + errmsg = insert_normal (cd, fields->f_cell, 0, 0, 9, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_COLNUM : + errmsg = insert_normal (cd, fields->f_colnum, 0, 0, 18, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_CONTNUM : + errmsg = insert_normal (cd, fields->f_contnum, 0, 0, 8, 9, 32, total_length, buffer); + break; + case MS1_OPERAND_CR : + errmsg = insert_normal (cd, fields->f_cr, 0, 0, 22, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_CTXDISP : + errmsg = insert_normal (cd, fields->f_ctxdisp, 0, 0, 5, 6, 32, total_length, buffer); + break; + case MS1_OPERAND_DUP : + errmsg = insert_normal (cd, fields->f_dup, 0, 0, 6, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_FBDISP : + errmsg = insert_normal (cd, fields->f_fbdisp, 0, 0, 15, 6, 32, total_length, buffer); + break; + case MS1_OPERAND_FBINCR : + errmsg = insert_normal (cd, fields->f_fbincr, 0, 0, 23, 4, 32, total_length, buffer); + break; + case MS1_OPERAND_FRDR : + errmsg = insert_normal (cd, fields->f_dr, 0|(1<f_drrr, 0|(1<f_sr1, 0|(1<f_sr2, 0|(1<f_id, 0, 0, 14, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_IMM16 : + { + long value = fields->f_imm16s; + value = ((value) + (0)); + errmsg = insert_normal (cd, value, 0|(1<f_imm16s; + value = ((value) + (0)); + errmsg = insert_normal (cd, value, 0|(1<f_imm16u, 0, 0, 15, 16, 32, total_length, buffer); + break; + case MS1_OPERAND_INCAMT : + errmsg = insert_normal (cd, fields->f_incamt, 0, 0, 19, 8, 32, total_length, buffer); + break; + case MS1_OPERAND_INCR : + errmsg = insert_normal (cd, fields->f_incr, 0, 0, 17, 6, 32, total_length, buffer); + break; + case MS1_OPERAND_LENGTH : + errmsg = insert_normal (cd, fields->f_length, 0, 0, 15, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_MASK : + errmsg = insert_normal (cd, fields->f_mask, 0, 0, 25, 16, 32, total_length, buffer); + break; + case MS1_OPERAND_MASK1 : + errmsg = insert_normal (cd, fields->f_mask1, 0, 0, 22, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_MODE : + errmsg = insert_normal (cd, fields->f_mode, 0, 0, 25, 2, 32, total_length, buffer); + break; + case MS1_OPERAND_PERM : + errmsg = insert_normal (cd, fields->f_perm, 0, 0, 25, 2, 32, total_length, buffer); + break; + case MS1_OPERAND_RBBC : + errmsg = insert_normal (cd, fields->f_rbbc, 0, 0, 25, 2, 32, total_length, buffer); + break; + case MS1_OPERAND_RC : + errmsg = insert_normal (cd, fields->f_rc, 0, 0, 15, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_RC1 : + errmsg = insert_normal (cd, fields->f_rc1, 0, 0, 11, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_RC2 : + errmsg = insert_normal (cd, fields->f_rc2, 0, 0, 6, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_RCNUM : + errmsg = insert_normal (cd, fields->f_rcnum, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_RDA : + errmsg = insert_normal (cd, fields->f_rda, 0, 0, 25, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_ROWNUM : + errmsg = insert_normal (cd, fields->f_rownum, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_ROWNUM1 : + errmsg = insert_normal (cd, fields->f_rownum1, 0, 0, 12, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_ROWNUM2 : + errmsg = insert_normal (cd, fields->f_rownum2, 0, 0, 9, 3, 32, total_length, buffer); + break; + case MS1_OPERAND_SIZE : + errmsg = insert_normal (cd, fields->f_size, 0, 0, 13, 14, 32, total_length, buffer); + break; + case MS1_OPERAND_TYPE : + errmsg = insert_normal (cd, fields->f_type, 0, 0, 21, 2, 32, total_length, buffer); + break; + case MS1_OPERAND_WR : + errmsg = insert_normal (cd, fields->f_wr, 0, 0, 24, 1, 32, total_length, buffer); + break; + case MS1_OPERAND_XMODE : + errmsg = insert_normal (cd, fields->f_xmode, 0, 0, 23, 1, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int ms1_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +ms1_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MS1_OPERAND_A23 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_a23); + break; + case MS1_OPERAND_BALL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_ball); + break; + case MS1_OPERAND_BALL2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_ball2); + break; + case MS1_OPERAND_BANKADDR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 13, 32, total_length, pc, & fields->f_bankaddr); + break; + case MS1_OPERAND_BRC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_brc); + break; + case MS1_OPERAND_BRC2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_brc2); + break; + case MS1_OPERAND_CBRB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cbrb); + break; + case MS1_OPERAND_CBS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 2, 32, total_length, pc, & fields->f_cbs); + break; + case MS1_OPERAND_CBX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_cbx); + break; + case MS1_OPERAND_CCB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_ccb); + break; + case MS1_OPERAND_CDB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cdb); + break; + case MS1_OPERAND_CELL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_cell); + break; + case MS1_OPERAND_COLNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_colnum); + break; + case MS1_OPERAND_CONTNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_contnum); + break; + case MS1_OPERAND_CR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cr); + break; + case MS1_OPERAND_CTXDISP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_ctxdisp); + break; + case MS1_OPERAND_DUP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_dup); + break; + case MS1_OPERAND_FBDISP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_fbdisp); + break; + case MS1_OPERAND_FBINCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 4, 32, total_length, pc, & fields->f_fbincr); + break; + case MS1_OPERAND_FRDR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dr); + break; + case MS1_OPERAND_FRDRRR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_drrr); + break; + case MS1_OPERAND_FRSR1 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_sr1); + break; + case MS1_OPERAND_FRSR2 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_sr2); + break; + case MS1_OPERAND_ID : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 1, 32, total_length, pc, & fields->f_id); + break; + case MS1_OPERAND_IMM16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16s = value; + } + break; + case MS1_OPERAND_IMM16O : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16s = value; + } + break; + case MS1_OPERAND_IMM16Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm16u); + break; + case MS1_OPERAND_INCAMT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 8, 32, total_length, pc, & fields->f_incamt); + break; + case MS1_OPERAND_INCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_incr); + break; + case MS1_OPERAND_LENGTH : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_length); + break; + case MS1_OPERAND_MASK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 16, 32, total_length, pc, & fields->f_mask); + break; + case MS1_OPERAND_MASK1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_mask1); + break; + case MS1_OPERAND_MODE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_mode); + break; + case MS1_OPERAND_PERM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_perm); + break; + case MS1_OPERAND_RBBC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_rbbc); + break; + case MS1_OPERAND_RC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_rc); + break; + case MS1_OPERAND_RC1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_rc1); + break; + case MS1_OPERAND_RC2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_rc2); + break; + case MS1_OPERAND_RCNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rcnum); + break; + case MS1_OPERAND_RDA : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_rda); + break; + case MS1_OPERAND_ROWNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rownum); + break; + case MS1_OPERAND_ROWNUM1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rownum1); + break; + case MS1_OPERAND_ROWNUM2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rownum2); + break; + case MS1_OPERAND_SIZE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 14, 32, total_length, pc, & fields->f_size); + break; + case MS1_OPERAND_TYPE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 2, 32, total_length, pc, & fields->f_type); + break; + case MS1_OPERAND_WR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_wr); + break; + case MS1_OPERAND_XMODE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_xmode); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const ms1_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const ms1_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int ms1_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma ms1_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +ms1_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case MS1_OPERAND_A23 : + value = fields->f_a23; + break; + case MS1_OPERAND_BALL : + value = fields->f_ball; + break; + case MS1_OPERAND_BALL2 : + value = fields->f_ball2; + break; + case MS1_OPERAND_BANKADDR : + value = fields->f_bankaddr; + break; + case MS1_OPERAND_BRC : + value = fields->f_brc; + break; + case MS1_OPERAND_BRC2 : + value = fields->f_brc2; + break; + case MS1_OPERAND_CBRB : + value = fields->f_cbrb; + break; + case MS1_OPERAND_CBS : + value = fields->f_cbs; + break; + case MS1_OPERAND_CBX : + value = fields->f_cbx; + break; + case MS1_OPERAND_CCB : + value = fields->f_ccb; + break; + case MS1_OPERAND_CDB : + value = fields->f_cdb; + break; + case MS1_OPERAND_CELL : + value = fields->f_cell; + break; + case MS1_OPERAND_COLNUM : + value = fields->f_colnum; + break; + case MS1_OPERAND_CONTNUM : + value = fields->f_contnum; + break; + case MS1_OPERAND_CR : + value = fields->f_cr; + break; + case MS1_OPERAND_CTXDISP : + value = fields->f_ctxdisp; + break; + case MS1_OPERAND_DUP : + value = fields->f_dup; + break; + case MS1_OPERAND_FBDISP : + value = fields->f_fbdisp; + break; + case MS1_OPERAND_FBINCR : + value = fields->f_fbincr; + break; + case MS1_OPERAND_FRDR : + value = fields->f_dr; + break; + case MS1_OPERAND_FRDRRR : + value = fields->f_drrr; + break; + case MS1_OPERAND_FRSR1 : + value = fields->f_sr1; + break; + case MS1_OPERAND_FRSR2 : + value = fields->f_sr2; + break; + case MS1_OPERAND_ID : + value = fields->f_id; + break; + case MS1_OPERAND_IMM16 : + value = fields->f_imm16s; + break; + case MS1_OPERAND_IMM16O : + value = fields->f_imm16s; + break; + case MS1_OPERAND_IMM16Z : + value = fields->f_imm16u; + break; + case MS1_OPERAND_INCAMT : + value = fields->f_incamt; + break; + case MS1_OPERAND_INCR : + value = fields->f_incr; + break; + case MS1_OPERAND_LENGTH : + value = fields->f_length; + break; + case MS1_OPERAND_MASK : + value = fields->f_mask; + break; + case MS1_OPERAND_MASK1 : + value = fields->f_mask1; + break; + case MS1_OPERAND_MODE : + value = fields->f_mode; + break; + case MS1_OPERAND_PERM : + value = fields->f_perm; + break; + case MS1_OPERAND_RBBC : + value = fields->f_rbbc; + break; + case MS1_OPERAND_RC : + value = fields->f_rc; + break; + case MS1_OPERAND_RC1 : + value = fields->f_rc1; + break; + case MS1_OPERAND_RC2 : + value = fields->f_rc2; + break; + case MS1_OPERAND_RCNUM : + value = fields->f_rcnum; + break; + case MS1_OPERAND_RDA : + value = fields->f_rda; + break; + case MS1_OPERAND_ROWNUM : + value = fields->f_rownum; + break; + case MS1_OPERAND_ROWNUM1 : + value = fields->f_rownum1; + break; + case MS1_OPERAND_ROWNUM2 : + value = fields->f_rownum2; + break; + case MS1_OPERAND_SIZE : + value = fields->f_size; + break; + case MS1_OPERAND_TYPE : + value = fields->f_type; + break; + case MS1_OPERAND_WR : + value = fields->f_wr; + break; + case MS1_OPERAND_XMODE : + value = fields->f_xmode; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +ms1_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case MS1_OPERAND_A23 : + value = fields->f_a23; + break; + case MS1_OPERAND_BALL : + value = fields->f_ball; + break; + case MS1_OPERAND_BALL2 : + value = fields->f_ball2; + break; + case MS1_OPERAND_BANKADDR : + value = fields->f_bankaddr; + break; + case MS1_OPERAND_BRC : + value = fields->f_brc; + break; + case MS1_OPERAND_BRC2 : + value = fields->f_brc2; + break; + case MS1_OPERAND_CBRB : + value = fields->f_cbrb; + break; + case MS1_OPERAND_CBS : + value = fields->f_cbs; + break; + case MS1_OPERAND_CBX : + value = fields->f_cbx; + break; + case MS1_OPERAND_CCB : + value = fields->f_ccb; + break; + case MS1_OPERAND_CDB : + value = fields->f_cdb; + break; + case MS1_OPERAND_CELL : + value = fields->f_cell; + break; + case MS1_OPERAND_COLNUM : + value = fields->f_colnum; + break; + case MS1_OPERAND_CONTNUM : + value = fields->f_contnum; + break; + case MS1_OPERAND_CR : + value = fields->f_cr; + break; + case MS1_OPERAND_CTXDISP : + value = fields->f_ctxdisp; + break; + case MS1_OPERAND_DUP : + value = fields->f_dup; + break; + case MS1_OPERAND_FBDISP : + value = fields->f_fbdisp; + break; + case MS1_OPERAND_FBINCR : + value = fields->f_fbincr; + break; + case MS1_OPERAND_FRDR : + value = fields->f_dr; + break; + case MS1_OPERAND_FRDRRR : + value = fields->f_drrr; + break; + case MS1_OPERAND_FRSR1 : + value = fields->f_sr1; + break; + case MS1_OPERAND_FRSR2 : + value = fields->f_sr2; + break; + case MS1_OPERAND_ID : + value = fields->f_id; + break; + case MS1_OPERAND_IMM16 : + value = fields->f_imm16s; + break; + case MS1_OPERAND_IMM16O : + value = fields->f_imm16s; + break; + case MS1_OPERAND_IMM16Z : + value = fields->f_imm16u; + break; + case MS1_OPERAND_INCAMT : + value = fields->f_incamt; + break; + case MS1_OPERAND_INCR : + value = fields->f_incr; + break; + case MS1_OPERAND_LENGTH : + value = fields->f_length; + break; + case MS1_OPERAND_MASK : + value = fields->f_mask; + break; + case MS1_OPERAND_MASK1 : + value = fields->f_mask1; + break; + case MS1_OPERAND_MODE : + value = fields->f_mode; + break; + case MS1_OPERAND_PERM : + value = fields->f_perm; + break; + case MS1_OPERAND_RBBC : + value = fields->f_rbbc; + break; + case MS1_OPERAND_RC : + value = fields->f_rc; + break; + case MS1_OPERAND_RC1 : + value = fields->f_rc1; + break; + case MS1_OPERAND_RC2 : + value = fields->f_rc2; + break; + case MS1_OPERAND_RCNUM : + value = fields->f_rcnum; + break; + case MS1_OPERAND_RDA : + value = fields->f_rda; + break; + case MS1_OPERAND_ROWNUM : + value = fields->f_rownum; + break; + case MS1_OPERAND_ROWNUM1 : + value = fields->f_rownum1; + break; + case MS1_OPERAND_ROWNUM2 : + value = fields->f_rownum2; + break; + case MS1_OPERAND_SIZE : + value = fields->f_size; + break; + case MS1_OPERAND_TYPE : + value = fields->f_type; + break; + case MS1_OPERAND_WR : + value = fields->f_wr; + break; + case MS1_OPERAND_XMODE : + value = fields->f_xmode; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void ms1_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void ms1_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +ms1_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case MS1_OPERAND_A23 : + fields->f_a23 = value; + break; + case MS1_OPERAND_BALL : + fields->f_ball = value; + break; + case MS1_OPERAND_BALL2 : + fields->f_ball2 = value; + break; + case MS1_OPERAND_BANKADDR : + fields->f_bankaddr = value; + break; + case MS1_OPERAND_BRC : + fields->f_brc = value; + break; + case MS1_OPERAND_BRC2 : + fields->f_brc2 = value; + break; + case MS1_OPERAND_CBRB : + fields->f_cbrb = value; + break; + case MS1_OPERAND_CBS : + fields->f_cbs = value; + break; + case MS1_OPERAND_CBX : + fields->f_cbx = value; + break; + case MS1_OPERAND_CCB : + fields->f_ccb = value; + break; + case MS1_OPERAND_CDB : + fields->f_cdb = value; + break; + case MS1_OPERAND_CELL : + fields->f_cell = value; + break; + case MS1_OPERAND_COLNUM : + fields->f_colnum = value; + break; + case MS1_OPERAND_CONTNUM : + fields->f_contnum = value; + break; + case MS1_OPERAND_CR : + fields->f_cr = value; + break; + case MS1_OPERAND_CTXDISP : + fields->f_ctxdisp = value; + break; + case MS1_OPERAND_DUP : + fields->f_dup = value; + break; + case MS1_OPERAND_FBDISP : + fields->f_fbdisp = value; + break; + case MS1_OPERAND_FBINCR : + fields->f_fbincr = value; + break; + case MS1_OPERAND_FRDR : + fields->f_dr = value; + break; + case MS1_OPERAND_FRDRRR : + fields->f_drrr = value; + break; + case MS1_OPERAND_FRSR1 : + fields->f_sr1 = value; + break; + case MS1_OPERAND_FRSR2 : + fields->f_sr2 = value; + break; + case MS1_OPERAND_ID : + fields->f_id = value; + break; + case MS1_OPERAND_IMM16 : + fields->f_imm16s = value; + break; + case MS1_OPERAND_IMM16O : + fields->f_imm16s = value; + break; + case MS1_OPERAND_IMM16Z : + fields->f_imm16u = value; + break; + case MS1_OPERAND_INCAMT : + fields->f_incamt = value; + break; + case MS1_OPERAND_INCR : + fields->f_incr = value; + break; + case MS1_OPERAND_LENGTH : + fields->f_length = value; + break; + case MS1_OPERAND_MASK : + fields->f_mask = value; + break; + case MS1_OPERAND_MASK1 : + fields->f_mask1 = value; + break; + case MS1_OPERAND_MODE : + fields->f_mode = value; + break; + case MS1_OPERAND_PERM : + fields->f_perm = value; + break; + case MS1_OPERAND_RBBC : + fields->f_rbbc = value; + break; + case MS1_OPERAND_RC : + fields->f_rc = value; + break; + case MS1_OPERAND_RC1 : + fields->f_rc1 = value; + break; + case MS1_OPERAND_RC2 : + fields->f_rc2 = value; + break; + case MS1_OPERAND_RCNUM : + fields->f_rcnum = value; + break; + case MS1_OPERAND_RDA : + fields->f_rda = value; + break; + case MS1_OPERAND_ROWNUM : + fields->f_rownum = value; + break; + case MS1_OPERAND_ROWNUM1 : + fields->f_rownum1 = value; + break; + case MS1_OPERAND_ROWNUM2 : + fields->f_rownum2 = value; + break; + case MS1_OPERAND_SIZE : + fields->f_size = value; + break; + case MS1_OPERAND_TYPE : + fields->f_type = value; + break; + case MS1_OPERAND_WR : + fields->f_wr = value; + break; + case MS1_OPERAND_XMODE : + fields->f_xmode = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +ms1_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case MS1_OPERAND_A23 : + fields->f_a23 = value; + break; + case MS1_OPERAND_BALL : + fields->f_ball = value; + break; + case MS1_OPERAND_BALL2 : + fields->f_ball2 = value; + break; + case MS1_OPERAND_BANKADDR : + fields->f_bankaddr = value; + break; + case MS1_OPERAND_BRC : + fields->f_brc = value; + break; + case MS1_OPERAND_BRC2 : + fields->f_brc2 = value; + break; + case MS1_OPERAND_CBRB : + fields->f_cbrb = value; + break; + case MS1_OPERAND_CBS : + fields->f_cbs = value; + break; + case MS1_OPERAND_CBX : + fields->f_cbx = value; + break; + case MS1_OPERAND_CCB : + fields->f_ccb = value; + break; + case MS1_OPERAND_CDB : + fields->f_cdb = value; + break; + case MS1_OPERAND_CELL : + fields->f_cell = value; + break; + case MS1_OPERAND_COLNUM : + fields->f_colnum = value; + break; + case MS1_OPERAND_CONTNUM : + fields->f_contnum = value; + break; + case MS1_OPERAND_CR : + fields->f_cr = value; + break; + case MS1_OPERAND_CTXDISP : + fields->f_ctxdisp = value; + break; + case MS1_OPERAND_DUP : + fields->f_dup = value; + break; + case MS1_OPERAND_FBDISP : + fields->f_fbdisp = value; + break; + case MS1_OPERAND_FBINCR : + fields->f_fbincr = value; + break; + case MS1_OPERAND_FRDR : + fields->f_dr = value; + break; + case MS1_OPERAND_FRDRRR : + fields->f_drrr = value; + break; + case MS1_OPERAND_FRSR1 : + fields->f_sr1 = value; + break; + case MS1_OPERAND_FRSR2 : + fields->f_sr2 = value; + break; + case MS1_OPERAND_ID : + fields->f_id = value; + break; + case MS1_OPERAND_IMM16 : + fields->f_imm16s = value; + break; + case MS1_OPERAND_IMM16O : + fields->f_imm16s = value; + break; + case MS1_OPERAND_IMM16Z : + fields->f_imm16u = value; + break; + case MS1_OPERAND_INCAMT : + fields->f_incamt = value; + break; + case MS1_OPERAND_INCR : + fields->f_incr = value; + break; + case MS1_OPERAND_LENGTH : + fields->f_length = value; + break; + case MS1_OPERAND_MASK : + fields->f_mask = value; + break; + case MS1_OPERAND_MASK1 : + fields->f_mask1 = value; + break; + case MS1_OPERAND_MODE : + fields->f_mode = value; + break; + case MS1_OPERAND_PERM : + fields->f_perm = value; + break; + case MS1_OPERAND_RBBC : + fields->f_rbbc = value; + break; + case MS1_OPERAND_RC : + fields->f_rc = value; + break; + case MS1_OPERAND_RC1 : + fields->f_rc1 = value; + break; + case MS1_OPERAND_RC2 : + fields->f_rc2 = value; + break; + case MS1_OPERAND_RCNUM : + fields->f_rcnum = value; + break; + case MS1_OPERAND_RDA : + fields->f_rda = value; + break; + case MS1_OPERAND_ROWNUM : + fields->f_rownum = value; + break; + case MS1_OPERAND_ROWNUM1 : + fields->f_rownum1 = value; + break; + case MS1_OPERAND_ROWNUM2 : + fields->f_rownum2 = value; + break; + case MS1_OPERAND_SIZE : + fields->f_size = value; + break; + case MS1_OPERAND_TYPE : + fields->f_type = value; + break; + case MS1_OPERAND_WR : + fields->f_wr = value; + break; + case MS1_OPERAND_XMODE : + fields->f_xmode = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +ms1_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & ms1_cgen_insert_handlers[0]; + cd->extract_handlers = & ms1_cgen_extract_handlers[0]; + + cd->insert_operand = ms1_cgen_insert_operand; + cd->extract_operand = ms1_cgen_extract_operand; + + cd->get_int_operand = ms1_cgen_get_int_operand; + cd->set_int_operand = ms1_cgen_set_int_operand; + cd->get_vma_operand = ms1_cgen_get_vma_operand; + cd->set_vma_operand = ms1_cgen_set_vma_operand; +} diff --git a/opcodes/ms1-opc.c b/opcodes/ms1-opc.c new file mode 100644 index 00000000000..d7c57becf64 --- /dev/null +++ b/opcodes/ms1-opc.c @@ -0,0 +1,896 @@ +/* Instruction opcode table for ms1. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ms1-desc.h" +#include "ms1-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +#include "safe-ctype.h" + +/* Special check to ensure that instruction exists for given machine. */ + +int +ms1_cgen_insn_supported (CGEN_CPU_DESC cd, + const CGEN_INSN *insn) +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + + /* No mach attribute? Assume it's supported for all machs. */ + if (machs == 0) + return 1; + + return ((machs & cd->machs) != 0); +} + +/* A better hash function for instruction mnemonics. */ + +unsigned int +ms1_asm_hash (const char* insn) +{ + unsigned int hash; + const char* m = insn; + + for (hash = 0; *m && ! ISSPACE (*m); m++) + hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); + + /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ + + return hash % CGEN_ASM_HASH_SIZE; +} + + +/* -- asm.c */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & ms1_cgen_ifld_table[MS1_##f] +#else +#define F(f) & ms1_cgen_ifld_table[MS1_/**/f] +#endif +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 32, 32, 0xff000fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addui ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldui ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_brlt ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jal ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dbnz ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ei ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_si ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = { + 32, 32, 0xff0fffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stw ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldctxt ATTRIBUTE_UNUSED = { + 32, 32, 0xff000e00, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_RC) }, { F (F_RCNUM) }, { F (F_UU_3_11) }, { F (F_CONTNUM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldfb ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16U) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_4_15) }, { F (F_RC) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_4_15) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcci ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcci ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbdr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_BALL2) }, { F (F_BRC2) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rcfbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrcfbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cbcast ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000380, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_UU_3_9) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dupcbcast ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_CELL) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfbi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_BANKADDR) }, { F (F_ROWNUM1) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfb ATTRIBUTE_UNUSED = { + 32, 32, 0xff000040, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_UU_1_6) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rcrisc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc080000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_UU_1_19) }, { F (F_COLNUM) }, { F (F_DRRR) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbinc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_INCAMT) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rcxmode ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_XMODE) }, { F (F_MASK1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_interleaver ATTRIBUTE_UNUSED = { + 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MODE) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ID) }, { F (F_SIZE) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfbinc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwfbinc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfbincr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwfbincr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbincs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_A23) }, { F (F_CR) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcbincs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbincrs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcbincrs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) MS1_OPERAND_##op +#else +#define OPERAND(op) MS1_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE ms1_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x0 } + }, +/* addu $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x2000000 } + }, +/* addi $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x1000000 } + }, +/* addui $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x3000000 } + }, +/* sub $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x4000000 } + }, +/* subu $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x6000000 } + }, +/* subi $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x5000000 } + }, +/* subui $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x7000000 } + }, +/* mul $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x8000000 } + }, +/* muli $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x9000000 } + }, +/* and $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x10000000 } + }, +/* andi $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x11000000 } + }, +/* or $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x12000000 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x12000000 } + }, +/* ori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x13000000 } + }, +/* xor $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x14000000 } + }, +/* xori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x15000000 } + }, +/* nand $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x16000000 } + }, +/* nandi $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x17000000 } + }, +/* nor $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x18000000 } + }, +/* nori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x19000000 } + }, +/* xnor $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x1a000000 } + }, +/* xnori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x1b000000 } + }, +/* ldui $frdr,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_ldui, { 0x1d000000 } + }, +/* lsl $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x20000000 } + }, +/* lsli $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x21000000 } + }, +/* lsr $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x22000000 } + }, +/* lsri $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x23000000 } + }, +/* asr $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x24000000 } + }, +/* asri $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x25000000 } + }, +/* brlt $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x31000000 } + }, +/* brle $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x33000000 } + }, +/* breq $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x35000000 } + }, +/* brne $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x3b000000 } + }, +/* jmp $imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM16O), 0 } }, + & ifmt_jmp, { 0x37000000 } + }, +/* jal $frdrrr,$frsr1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), 0 } }, + & ifmt_jal, { 0x38000000 } + }, +/* dbnz $frsr1,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (IMM16O), 0 } }, + & ifmt_dbnz, { 0x3d000000 } + }, +/* ei */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ei, { 0x60000000 } + }, +/* di */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ei, { 0x62000000 } + }, +/* si $frdrrr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), 0 } }, + & ifmt_si, { 0x64000000 } + }, +/* reti $frsr1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), 0 } }, + & ifmt_reti, { 0x66000000 } + }, +/* ldw $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x41000000 } + }, +/* stw $frsr2,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_stw, { 0x43000000 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x68000000 } + }, +/* iflush */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x6a000000 } + }, +/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RC), ',', '#', OP (RCNUM), ',', '#', OP (CONTNUM), 0 } }, + & ifmt_ldctxt, { 0x80000000 } + }, +/* ldfb $frsr1,$frsr2,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_ldfb, { 0x84000000 } + }, +/* stfb $frsr1,$frsr2,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_ldfb, { 0x88000000 } + }, +/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcb, { 0x8c000000 } + }, +/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcb, { 0x90000000 } + }, +/* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0x94000000 } + }, +/* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0x98000000 } + }, +/* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0x9c000000 } + }, +/* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0xa0000000 } + }, +/* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xa4000000 } + }, +/* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xa8000000 } + }, +/* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xac000000 } + }, +/* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xb0000000 } + }, +/* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (BALL2), ',', '#', OP (BRC2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbdr, { 0xb4000000 } + }, +/* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_rcfbcb, { 0xb8000000 } + }, +/* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mrcfbcb, { 0xbc000000 } + }, +/* cbcast #$mask,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_cbcast, { 0xc0000000 } + }, +/* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (CELL), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_dupcbcast, { 0xc4000000 } + }, +/* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (BANKADDR), ',', '#', OP (ROWNUM1), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfbi, { 0xc8000000 } + }, +/* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfb, { 0xcc000000 } + }, +/* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', '#', OP (RBBC), ',', OP (FRSR1), ',', '#', OP (COLNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_rcrisc, { 0xd0000000 } + }, +/* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (INCAMT), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbinc, { 0xd4000000 } + }, +/* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (XMODE), ',', '#', OP (MASK1), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_rcxmode, { 0xd8000000 } + }, +/* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (MODE), ',', OP (FRSR2), ',', '#', OP (ID), ',', '#', OP (SIZE), 0 } }, + & ifmt_interleaver, { 0xdc000000 } + }, +/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfbinc, { 0xe0000000 } + }, +/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mwfbinc, { 0xe4000000 } + }, +/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfbincr, { 0xe8000000 } + }, +/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mwfbincr, { 0xec000000 } + }, +/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (PERM), ',', '#', OP (A23), ',', '#', OP (CR), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbincs, { 0xf0000000 } + }, +/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcbincs, { 0xf4000000 } + }, +/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbincrs, { 0xf8000000 } + }, +/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (PERM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcbincrs, { 0xfc000000 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & ms1_cgen_ifld_table[MS1_##f] +#else +#define F(f) & ms1_cgen_ifld_table[MS1_/**/f] +#endif +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) MS1_OPERAND_##op +#else +#define OPERAND(op) MS1_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE ms1_cgen_macro_insn_table[] = +{ +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE ms1_cgen_macro_insn_opcode_table[] = +{ +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (fields, size) + CGEN_FIELDS *fields; + int size; +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +ms1_cgen_init_opcode_table (cd) + CGEN_CPU_DESC cd; +{ + int i; + int num_macros = (sizeof (ms1_cgen_macro_insn_table) / + sizeof (ms1_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & ms1_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & ms1_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + ms1_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & ms1_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + ms1_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/ms1-opc.h b/opcodes/ms1-opc.h new file mode 100644 index 00000000000..5ac13577bef --- /dev/null +++ b/opcodes/ms1-opc.h @@ -0,0 +1,169 @@ +/* Instruction opcode header for ms1. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MS1_OPC_H +#define MS1_OPC_H + +/* -- opc.h */ + +/* Check applicability of instructions against machines. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) + +#define CGEN_ASM_HASH_SIZE 127 +#define CGEN_ASM_HASH(insn) ms1_asm_hash (insn) + +extern unsigned int ms1_asm_hash (const char *); + +extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + + +/* -- opc.c */ +/* Enum declaration for ms1 instruction types. */ +typedef enum cgen_insn_type { + MS1_INSN_INVALID, MS1_INSN_ADD, MS1_INSN_ADDU, MS1_INSN_ADDI + , MS1_INSN_ADDUI, MS1_INSN_SUB, MS1_INSN_SUBU, MS1_INSN_SUBI + , MS1_INSN_SUBUI, MS1_INSN_MUL, MS1_INSN_MULI, MS1_INSN_AND + , MS1_INSN_ANDI, MS1_INSN_OR, MS1_INSN_NOP, MS1_INSN_ORI + , MS1_INSN_XOR, MS1_INSN_XORI, MS1_INSN_NAND, MS1_INSN_NANDI + , MS1_INSN_NOR, MS1_INSN_NORI, MS1_INSN_XNOR, MS1_INSN_XNORI + , MS1_INSN_LDUI, MS1_INSN_LSL, MS1_INSN_LSLI, MS1_INSN_LSR + , MS1_INSN_LSRI, MS1_INSN_ASR, MS1_INSN_ASRI, MS1_INSN_BRLT + , MS1_INSN_BRLE, MS1_INSN_BREQ, MS1_INSN_BRNE, MS1_INSN_JMP + , MS1_INSN_JAL, MS1_INSN_DBNZ, MS1_INSN_EI, MS1_INSN_DI + , MS1_INSN_SI, MS1_INSN_RETI, MS1_INSN_LDW, MS1_INSN_STW + , MS1_INSN_BREAK, MS1_INSN_IFLUSH, MS1_INSN_LDCTXT, MS1_INSN_LDFB + , MS1_INSN_STFB, MS1_INSN_FBCB, MS1_INSN_MFBCB, MS1_INSN_FBCCI + , MS1_INSN_FBRCI, MS1_INSN_FBCRI, MS1_INSN_FBRRI, MS1_INSN_MFBCCI + , MS1_INSN_MFBRCI, MS1_INSN_MFBCRI, MS1_INSN_MFBRRI, MS1_INSN_FBCBDR + , MS1_INSN_RCFBCB, MS1_INSN_MRCFBCB, MS1_INSN_CBCAST, MS1_INSN_DUPCBCAST + , MS1_INSN_WFBI, MS1_INSN_WFB, MS1_INSN_RCRISC, MS1_INSN_FBCBINC + , MS1_INSN_RCXMODE, MS1_INSN_INTERLEAVER, MS1_INSN_WFBINC, MS1_INSN_MWFBINC + , MS1_INSN_WFBINCR, MS1_INSN_MWFBINCR, MS1_INSN_FBCBINCS, MS1_INSN_MFBCBINCS + , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID MS1_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) MS1_INSN_MFBCBINCRS + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_msys; + long f_opc; + long f_imm; + long f_uu24; + long f_sr1; + long f_sr2; + long f_dr; + long f_drrr; + long f_imm16u; + long f_imm16s; + long f_imm16a; + long f_uu4a; + long f_uu4b; + long f_uu12; + long f_uu16; + long f_msopc; + long f_uu_26_25; + long f_mask; + long f_bankaddr; + long f_rda; + long f_uu_2_25; + long f_rbbc; + long f_perm; + long f_mode; + long f_uu_1_24; + long f_wr; + long f_fbincr; + long f_uu_2_23; + long f_xmode; + long f_a23; + long f_mask1; + long f_cr; + long f_type; + long f_incamt; + long f_cbs; + long f_uu_1_19; + long f_ball; + long f_colnum; + long f_brc; + long f_incr; + long f_fbdisp; + long f_uu_4_15; + long f_length; + long f_uu_1_15; + long f_rc; + long f_rcnum; + long f_rownum; + long f_cbx; + long f_id; + long f_size; + long f_rownum1; + long f_uu_3_11; + long f_rc1; + long f_ccb; + long f_cbrb; + long f_cdb; + long f_rownum2; + long f_cell; + long f_uu_3_9; + long f_contnum; + long f_uu_1_6; + long f_dup; + long f_rc2; + long f_ctxdisp; + long f_msysfrsr2; + long f_brc2; + long f_ball2; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* MS1_OPC_H */