From: Korey Sewell <ksewell@umich.edu>
Date: Sat, 23 Jun 2007 01:09:35 +0000 (-0400)
Subject: FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand... 
X-Git-Tag: m5_2.0_beta4~306
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac19e0c5050219cbb0579a319fa3fab5cf92835d;p=gem5.git

FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...

src/arch/isa_parser.py:
    add back deleted writeback in Control Operand

--HG--
extra : convert_revision : dba11af220a1281fa53f79d87e4f8752bdfc56db
---

diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 95c57af2f..754a64fdb 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -25,7 +25,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Steve Reinhardt
-#          Gabe Black
 #          Korey Sewell
 
 import os
@@ -1411,6 +1410,9 @@ class ControlRegOperand(Operand):
             error(0, 'Attempt to write control register as FP')
         wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
              (self.dest_reg_idx, self.base_name)
+        wb += 'if (traceData) { traceData->setData(%s); }' % \
+              self.base_name
+        return wb
 
 class ControlBitfieldOperand(ControlRegOperand):
     def makeRead(self):