From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 17:56:00 +0000 (-0800)
Subject: Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
X-Git-Tag: working-ls180~780^2~34
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac24a23e31f2da76f8b976cd89b9ec6fadf15374;p=yosys.git

Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
---

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 42f1068ad..d5e69a241 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -29,3 +29,4 @@ $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
 $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
+$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v
new file mode 100644
index 000000000..c0c5dc2fd
--- /dev/null
+++ b/techlibs/common/abc9_model.v
@@ -0,0 +1,10 @@
+module \$__ABC9_FF_ (input D, output Q);
+endmodule
+
+(* abc9_box *)
+module \$__ABC9_DELAY (input I, output O);
+  parameter DELAY = 0;
+  specify
+    (I => O) = DELAY;
+  endspecify
+endmodule