From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Wed, 9 Feb 2022 04:35:05 +0000 (+0100)
Subject: ecp5: Fix DPR16X4 sim model.
X-Git-Tag: yosys-0.15~33
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac2bb70b5287af66c7bc6b7ed532575c1955c75e;p=yosys.git

ecp5: Fix DPR16X4 sim model.
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 357fd9173..a5f905cf8 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -204,7 +204,7 @@ module TRELLIS_DPR16X4 (
 	integer i;
 	initial begin
 		for (i = 0; i < 16; i = i + 1)
-			mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
+			mem[i] <= INITVAL[4*i +: 4];
 	end
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;