From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 14 Nov 2006 06:13:26 +0000 (-0500)
Subject: Update phase param in the .py file for the cpus
X-Git-Tag: m5_2.0_beta2~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac309071afe9d28e4635337c1c645a8cfc526a0f;p=gem5.git

Update phase param in the .py file for the cpus

--HG--
extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
---

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2f702a4bf..8037c90af 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,6 +47,7 @@ class BaseCPU(SimObject):
         "defer registration with system (for sampling)")
 
     clock = Param.Clock(Parent.clock, "clock speed")
+    phase = Param.Latency("0ns", "clock phase")
 
     _mem_ports = []