From: Korey Sewell <ksewell@umich.edu>
Date: Sat, 27 Mar 2010 05:40:05 +0000 (-0400)
Subject: inorder: write-hints bug fix
X-Git-Tag: stable_2012_02_02~1439
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac316d45e8818679efae8559eace010ae0487a99;p=gem5.git

inorder: write-hints bug fix
make sure to only read 1 src reg. for write-hint and any other similar
'store' instruction. Reading the source reg when its not necessary
can cause the simulator to read from uninitialized values
---

diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc
index 8ff26dce2..397170163 100644
--- a/src/cpu/inorder/pipeline_traits.cc
+++ b/src/cpu/inorder/pipeline_traits.cc
@@ -116,7 +116,9 @@ bool createBackEndSchedule(DynInstPtr &inst)
     if ( inst->isLoad() ) {
         M->needs(DCache, CacheUnit::InitiateReadData);
     } else if ( inst->isStore() ) {
-        M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+        if ( inst->numSrcRegs() >= 2 ) {            
+            M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+        }        
         M->needs(AGEN, AGENUnit::GenerateAddr);
         M->needs(DCache, CacheUnit::InitiateWriteData);
     }