From: Ali Saidi <saidi@eecs.umich.edu>
Date: Tue, 30 Jan 2007 23:27:04 +0000 (-0500)
Subject: add fsr to the list of registers we are interested in
X-Git-Tag: m5_2.0_beta3~227^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac36fb6e64dadb9eef5c48863b42969a61bbdaec;p=gem5.git

add fsr to the list of registers we are interested in

--HG--
extra : convert_revision : 2cc0d0144abab264aa0ec8c07242cdab2dffd4f8
---

diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 85b08ee32..e34ae3731 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -307,6 +307,7 @@ Trace::InstRecord::dump(ostream &outs)
         bool diffHtba = false;
         bool diffPstate = false;
         bool diffY = false;
+        bool diffFsr = false;
         bool diffCcr = false;
         bool diffTl = false;
         bool diffGl = false;
@@ -410,6 +411,8 @@ Trace::InstRecord::dump(ostream &outs)
                     if(shared_data->y !=
                             thread->readIntReg(NumIntArchRegs + 1))
                         diffY = true;
+                    if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR))
+                        diffFsr = true;
                     //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
                     if(shared_data->ccr !=
                             thread->readIntReg(NumIntArchRegs + 2))
@@ -450,8 +453,8 @@ Trace::InstRecord::dump(ostream &outs)
                     if ((diffPC || diffCC || diffInst || diffIntRegs ||
                          diffFpRegs || diffTpc || diffTnpc || diffTstate ||
                          diffTt || diffHpstate || diffHtstate || diffHtba ||
-                         diffPstate || diffY || diffCcr || diffTl || diffGl ||
-                         diffAsi || diffPil || diffCwp || diffCansave ||
+                         diffPstate || diffY || diffCcr || diffTl || diffFsr ||
+                         diffGl || diffAsi || diffPil || diffCwp || diffCansave ||
                          diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
                         && !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
                         && !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
@@ -487,6 +490,8 @@ Trace::InstRecord::dump(ostream &outs)
                             outs << " [Pstate]";
                         if (diffY)
                             outs << " [Y]";
+                        if (diffFsr)
+                            outs << " [FSR]";
                         if (diffCcr)
                             outs << " [Ccr]";
                         if (diffTl)
@@ -556,6 +561,9 @@ Trace::InstRecord::dump(ostream &outs)
                                 //thread->readMiscReg(MISCREG_Y),
                                 thread->readIntReg(NumIntArchRegs + 1),
                                 shared_data->y);
+                        printRegPair(outs, "FSR",
+                                thread->readMiscReg(MISCREG_FSR),
+                                shared_data->fsr);
                         printRegPair(outs, "Ccr",
                                 //thread->readMiscReg(MISCREG_CCR),
                                 thread->readIntReg(NumIntArchRegs + 2),
diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h
index 81714f769..373dc5cdc 100644
--- a/src/cpu/m5legion_interface.h
+++ b/src/cpu/m5legion_interface.h
@@ -30,7 +30,7 @@
 
 #include <unistd.h>
 
-#define VERSION         0xA1000008
+#define VERSION         0xA1000009
 #define OWN_M5          0x000000AA
 #define OWN_LEGION      0x00000055
 
@@ -61,6 +61,7 @@ typedef struct {
     uint16_t pstate;
 
     uint64_t y;
+    uint64_t fsr;
     uint8_t ccr;
     uint8_t tl;
     uint8_t gl;