From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Mar 2020 16:54:29 +0000 (+0000)
Subject: dewildcard cache.py
X-Git-Tag: div_pipeline~1712
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac5f6c5860d993c2fa55a8fc534400571e1136c0;p=soc.git

dewildcard cache.py
---

diff --git a/src/soc/minerva/cache.py b/src/soc/minerva/cache.py
index 5cdc1e89..47442911 100644
--- a/src/soc/minerva/cache.py
+++ b/src/soc/minerva/cache.py
@@ -1,5 +1,6 @@
-from nmigen import *
-from nmigen.asserts import *
+from nmigen import (Elaboratable, Module, Const, Signal, Record, Array,
+                    Mux, Memory)
+from nmigen.asserts import Assume, Initial
 from nmigen.lib.coding import Encoder
 from nmigen.utils import log2_int