From: lkcl Date: Tue, 3 Sep 2019 16:12:46 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~4166 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac63dffc110c6a5c6ac242ec2bcd3238b2991b53;p=libreriscv.git --- diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn index ace9b7f50..6ad14d4a8 100644 --- a/simple_v_extension/vblock_format/discussion.mdwn +++ b/simple_v_extension/vblock_format/discussion.mdwn @@ -39,7 +39,7 @@ When Twin-SVP Mode is enabled (0b11), a *second* P48 prefix follows after a P48- in the VBLOCK (another 16 bits after the 32 bit P48/P64 block), which applies vector-context from the *second* instruction's registers. The reason why Twin-SVP's prefix is only P48 is because P64 can change VL and MVL. It makes no srnse to try to reset VL/MVL twice in succession. -VL/MVL from a P64 prefix is applied as if a [[specification/sv.setvl]] instruction had been executed as a hidden (first, implicit) instruction in the VBLOCK. +VL/MVL from a P64 prefix is applied as if a [[specification/sv.setvl]] instruction had been executed as a hidden (first, implicit) instruction in the VBLOCK. This *includes* modification of SV CSR STATE. # Rules