From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 1 Jan 2020 06:54:56 +0000 (-0800)
Subject: attributes.count() -> get_bool_attribute()
X-Git-Tag: working-ls180~881^2^2~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac808c5e2aa0fbcfb5b56160131fcc61ba13da05;p=yosys.git

attributes.count() -> get_bool_attribute()
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index be900f0e7..77659b4d8 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -284,7 +284,7 @@ struct XAigerWriter
 
                                         toposort.node(cell->name);
 
-                                        if (inst_module->attributes.count("\\abc9_flop"))
+                                        if (inst_module->get_bool_attribute("\\abc9_flop"))
                                                 flop_boxes.push_back(cell);
                                         continue;
                                 }
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3c53a5223..d6c8260b2 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 			}
 
 			RTLIL::Module* box_module = design->module(mapped_cell->type);
-			auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
+			auto abc9_flop = box_module && box_module->get_bool_attribute("\\abc9_flop");
 			for (auto &conn : mapped_cell->connections()) {
 				RTLIL::SigSpec newsig;
 				for (auto c : conn.second.chunks()) {
@@ -988,7 +988,7 @@ struct Abc9Pass : public Pass {
 
 			for (auto cell : all_cells) {
 				auto inst_module = design->module(cell->type);
-				if (!inst_module || !inst_module->attributes.count("\\abc9_flop")
+				if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop")
 						|| cell->get_bool_attribute("\\abc9_keep"))
 					continue;